[Mesa-dev] [PATCH 1/2] radeon/llvm: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP pattern

[Vincent Lejeune]

---
 lib/Target/AMDGPU/R600Instructions.td | 4 ++--
 lib/Target/AMDGPU/SIInstructions.td   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 9259680..d75c32e 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -898,8 +898,8 @@ class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP <
   inst, "RECIP_CLAMPED", []
 >;
 
-class RECIP_IEEE_Common <bits<11> inst> : R600_1OP_Helper <
-  inst, "RECIP_IEEE", int_AMDGPU_rcp
+class RECIP_IEEE_Common <bits<11> inst> : R600_1OP <
+  inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
 >;
 
 class RECIP_UINT_Common <bits<11> inst> : R600_1OP_Helper <
diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index cb94381..2354b2e 100644
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -609,7 +609,7 @@ defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", []>;
 defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>;
 defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>;
 defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32",
-  [(set VReg_32:$dst, (int_AMDGPU_rcp AllReg_32:$src0))]
+  [(set VReg_32:$dst, (fdiv FP_ONE, AllReg_32:$src0))]
 >;
 defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>;
 defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>;
-- 
1.8.0.1