[Mesa-dev] [PATCH V4 3/6] i965: fs: fix gen6+ math operands in one place

[Chris Forbes]

V4: Fix various style nits as pointed out by Eric, and expand IMM
operands on both Gen6 and Gen7.

Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
---
 src/mesa/drivers/dri/i965/brw_fs.cpp | 60 +++++++++++++++++++-----------------
 src/mesa/drivers/dri/i965/brw_fs.h   |  1 +
 2 files changed, 33 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 9ed9163..7d66115 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -942,6 +942,33 @@ fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
    return reg;
 }
 
+fs_reg
+fs_visitor::fix_math_operand(fs_reg src)
+{
+   /* Can't do hstride == 0 args on gen6 math, so expand it out. We
+    * might be able to do better by doing execsize = 1 math and then
+    * expanding that result out, but we would need to be careful with
+    * masking.
+    *
+    * The hardware ignores source modifiers (negate and abs) on math
+    * instructions, so we also move to a temp to set those up.
+    */
+
+   if (intel->gen == 6 && src.file != UNIFORM && src.file != IMM && !src.abs && !src.negate)
+      return src;
+
+   /* Gen7 relaxes most of the above restrictions, but still can't use IMM
+    * operands to math */
+
+   if (intel->gen >= 7 && src.file != IMM)
+      return src;
+
+   fs_reg expanded = fs_reg(this, glsl_type::float_type);
+   expanded.type = src.type;
+   emit(BRW_OPCODE_MOV, expanded, src);
+   return expanded;
+}
+
 fs_inst *
 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
 {
@@ -967,13 +994,8 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
     * Gen 6 hardware ignores source modifiers (negate and abs) on math
     * instructions, so we also move to a temp to set those up.
     */
-   if (intel->gen == 6 && (src.file == UNIFORM ||
-			   src.abs ||
-			   src.negate)) {
-      fs_reg expanded = fs_reg(this, glsl_type::float_type);
-      emit(BRW_OPCODE_MOV, expanded, src);
-      src = expanded;
-   }
+   if (intel->gen >= 6)
+      src = fix_math_operand(src);
 
    fs_inst *inst = emit(opcode, dst, src);
 
@@ -1001,27 +1023,9 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
       return NULL;
    }
 
-   if (intel->gen >= 7) {
-      inst = emit(opcode, dst, src0, src1);
-   } else if (intel->gen == 6) {
-      /* Can't do hstride == 0 args to gen6 math, so expand it out.
-       *
-       * The hardware ignores source modifiers (negate and abs) on math
-       * instructions, so we also move to a temp to set those up.
-       */
-      if (src0.file == UNIFORM || src0.abs || src0.negate) {
-	 fs_reg expanded = fs_reg(this, glsl_type::float_type);
-	 expanded.type = src0.type;
-	 emit(BRW_OPCODE_MOV, expanded, src0);
-	 src0 = expanded;
-      }
-
-      if (src1.file == UNIFORM || src1.abs || src1.negate) {
-	 fs_reg expanded = fs_reg(this, glsl_type::float_type);
-	 expanded.type = src1.type;
-	 emit(BRW_OPCODE_MOV, expanded, src1);
-	 src1 = expanded;
-      }
+   if (intel->gen >= 6) {
+      src0 = fix_math_operand(src0);
+      src1 = fix_math_operand(src1);
 
       inst = emit(opcode, dst, src0, src1);
    } else {
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 00ba334..07cace5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -327,6 +327,7 @@ public:
 			      fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 			      fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
+   fs_reg fix_math_operand(fs_reg src);
    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
    void emit_minmax(uint32_t conditionalmod, fs_reg dst,
-- 
1.8.0.1