[Mesa-dev] [PATCH] AMDGPU/SI: Only allow selecting VGPRs with V_CNDMASK_B32.

[Tom Stellard]

On Thu, Dec 06, 2012 at 11:55:15AM +0100, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
> 
> VALU instructions can only read from one SGPR, and that's the condition code
> mask in this case.
> 
> Fixes a number of radeonsi piglit regressions from Vincent's max/min changes
> (which means the matching to AMDGPUfmax/min doesn't work for some reason).

This looks good to me, though we should investigate why the AMDGPUfmax/min nodes
aren't being matched.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> 
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
> ---
>  lib/Target/AMDGPU/SIInstructions.td |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
> index 3564ec3..ea8de91 100644
> --- a/lib/Target/AMDGPU/SIInstructions.td
> +++ b/lib/Target/AMDGPU/SIInstructions.td
> @@ -764,15 +764,15 @@ def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
>  }
>  
>  def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
> -  (ins AllReg_32:$src0, AllReg_32:$src1, SReg_1:$src2, InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
> +  (ins VReg_32:$src0, VReg_32:$src1, SReg_1:$src2, InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
>    "V_CNDMASK_B32_e64",
> -  [(set (i32 VReg_32:$dst), (select SReg_1:$src2, AllReg_32:$src1, AllReg_32:$src0))]
> +  [(set (i32 VReg_32:$dst), (select SReg_1:$src2, VReg_32:$src1, VReg_32:$src0))]
>  >;
>  
>  //f32 pattern for V_CNDMASK_B32_e64
>  def : Pat <
> -  (f32 (select SReg_1:$src2, AllReg_32:$src1, AllReg_32:$src0)),
> -  (V_CNDMASK_B32_e64 AllReg_32:$src0, AllReg_32:$src1, SReg_1:$src2)
> +  (f32 (select SReg_1:$src2, VReg_32:$src1, VReg_32:$src0)),
> +  (V_CNDMASK_B32_e64 VReg_32:$src0, VReg_32:$src1, SReg_1:$src2)
>  >;
>  
>  defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;
> -- 
> 1.7.10.4
> 
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