[Mesa-dev] [PATCH 2/8] i965: Correct the name and usage of the flag subregister number field.

[Eric Anholt]

We've been calling it a register number, it's actually the subregister,
and things will get confusing once we start using it if it isn't fixed.
---
 src/mesa/drivers/dri/i965/brw_disasm.c      |    4 ++--
 src/mesa/drivers/dri/i965/brw_eu_compact.c  |    4 ++--
 src/mesa/drivers/dri/i965/brw_structs.h     |   10 +++++-----
 src/mesa/drivers/dri/i965/test_eu_compact.c |   12 ++++++------
 4 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 9246dee..1f3aeca 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -1049,8 +1049,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
 	string (file, "(");
 	err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
 	string (file, "f0");
-	if (inst->bits2.da1.flag_reg_nr)
-	    format (file, ".%d", inst->bits2.da1.flag_reg_nr);
+	if (inst->bits2.da1.flag_subreg_nr)
+	    format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
 	if (inst->header.access_mode == BRW_ALIGN_1)
 	    err |= control (file, "predicate control align1", pred_ctrl_align1,
 			    inst->header.predicate_control, NULL);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 90d1cdd..5d77f18 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -482,7 +482,7 @@ brw_try_compact_instruction(struct brw_compile *p,
    temp.dw0.acc_wr_control = src->header.acc_wr_control;
    temp.dw0.conditionalmod = src->header.destreg__conditionalmod;
    if (intel->gen <= 6)
-      temp.dw0.flag_reg_nr = src->bits2.da1.flag_reg_nr;
+      temp.dw0.flag_subreg_nr = src->bits2.da1.flag_subreg_nr;
    temp.dw0.cmpt_ctrl = 1;
    if (!set_src0_index(&temp, src))
       return false;
@@ -570,7 +570,7 @@ brw_uncompact_instruction(struct intel_context *intel,
    dst->header.acc_wr_control = src->dw0.acc_wr_control;
    dst->header.destreg__conditionalmod = src->dw0.conditionalmod;
    if (intel->gen <= 6)
-      dst->bits2.da1.flag_reg_nr = src->dw0.flag_reg_nr;
+      dst->bits2.da1.flag_subreg_nr = src->dw0.flag_subreg_nr;
    set_uncompacted_src0(dst, src);
    set_uncompacted_src1(dst, src);
    dst->bits1.da1.dest_reg_nr = src->dw1.dst_reg_nr;
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 64bc161..ac817b9 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1064,7 +1064,7 @@ struct brw_instruction
 	 GLuint src0_horiz_stride:2;
 	 GLuint src0_width:3;
 	 GLuint src0_vert_stride:4;
-	 GLuint flag_reg_nr:1;
+	 GLuint flag_subreg_nr:1;
 	 GLuint pad:6;
       } da1;
 
@@ -1078,7 +1078,7 @@ struct brw_instruction
 	 GLuint src0_horiz_stride:2;
 	 GLuint src0_width:3;
 	 GLuint src0_vert_stride:4;
-	 GLuint flag_reg_nr:1;
+	 GLuint flag_subreg_nr:1;
 	 GLuint pad:6;	
       } ia1;
 
@@ -1095,7 +1095,7 @@ struct brw_instruction
 	 GLuint src0_swz_w:2;
 	 GLuint pad0:1;
 	 GLuint src0_vert_stride:4;
-	 GLuint flag_reg_nr:1;
+	 GLuint flag_subreg_nr:1;
 	 GLuint pad1:6;
       } da16;
 
@@ -1112,7 +1112,7 @@ struct brw_instruction
 	 GLuint src0_swz_w:2;
 	 GLuint pad0:1;
 	 GLuint src0_vert_stride:4;
-	 GLuint flag_reg_nr:1;
+	 GLuint flag_subreg_nr:1;
 	 GLuint pad1:6;
       } ia16;
 
@@ -1545,7 +1545,7 @@ struct brw_compact_instruction {
       unsigned sub_reg_index:5;   /* 18-22 */
       unsigned acc_wr_control:1;  /* 23-23 */
       unsigned conditionalmod:4;  /* 24-27 */
-      unsigned flag_reg_nr:1;     /* 28-28 */
+      unsigned flag_subreg_nr:1;     /* 28-28 */
       unsigned cmpt_ctrl:1;       /* 29-29 */
       unsigned src0_index:2;      /* 30-31 */
    } dw0;
diff --git a/src/mesa/drivers/dri/i965/test_eu_compact.c b/src/mesa/drivers/dri/i965/test_eu_compact.c
index 73351c3..41a5ef5 100644
--- a/src/mesa/drivers/dri/i965/test_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/test_eu_compact.c
@@ -214,7 +214,7 @@ gen_PLN_MRF_GRF_GRF(struct brw_compile *p)
 }
 
 static void
-gen_f0_MOV_GRF_GRF(struct brw_compile *p)
+gen_f0_0_MOV_GRF_GRF(struct brw_compile *p)
 {
    struct brw_reg g0 = brw_vec8_grf(0, 0);
    struct brw_reg g2 = brw_vec8_grf(2, 0);
@@ -225,19 +225,19 @@ gen_f0_MOV_GRF_GRF(struct brw_compile *p)
    brw_pop_insn_state(p);
 }
 
-/* The handling of f1 vs f0 changes between gen6 and gen7.  Explicitly test
+/* The handling of f0.1 vs f0.0 changes between gen6 and gen7.  Explicitly test
  * it, so that we run the fuzzing can run over all the other bits that might
  * interact with it.
  */
 static void
-gen_f1_MOV_GRF_GRF(struct brw_compile *p)
+gen_f0_1_MOV_GRF_GRF(struct brw_compile *p)
 {
    struct brw_reg g0 = brw_vec8_grf(0, 0);
    struct brw_reg g2 = brw_vec8_grf(2, 0);
 
    brw_push_insn_state(p);
    brw_set_predicate_control(p, true);
-   current_insn(p)->bits2.da1.flag_reg_nr = 1;
+   current_insn(p)->bits2.da1.flag_subreg_nr = 1;
    brw_MOV(p, g0, g2);
    brw_pop_insn_state(p);
 }
@@ -252,8 +252,8 @@ struct {
    { gen_ADD_MRF_GRF_GRF },
    { gen_ADD_vec1_GRF_GRF_GRF },
    { gen_PLN_MRF_GRF_GRF },
-   { gen_f0_MOV_GRF_GRF },
-   { gen_f1_MOV_GRF_GRF },
+   { gen_f0_0_MOV_GRF_GRF },
+   { gen_f0_1_MOV_GRF_GRF },
 };
 
 static bool
-- 
1.7.10.4