[Mesa-dev] [PATCH 4/5] R600: Improve assembly output for VTX instructions

[Tom Stellard]

From: Tom Stellard <thomas.stellard at amd.com>

---
 lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp |  2 ++
 lib/Target/AMDGPU/R600Instructions.td               | 14 +++++++++-----
 test/CodeGen/R600/load.constant_addrspace.f32.ll    |  2 +-
 test/CodeGen/R600/load.i8.ll                        |  2 +-
 4 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
index 7e1064e..e6c550b 100644
--- a/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
+++ b/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
@@ -43,6 +43,8 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) {
   printOperand(MI, OpNo, O);
+  O  << ", ";
+  printOperand(MI, OpNo + 1, O);
 }
 
 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 092dd8c..41735a8 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -56,6 +56,7 @@ class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
 
 def MEMxi : Operand<iPTR> {
   let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
+  let PrintMethod = "printMemOperand";
 }
 
 def MEMrr : Operand<iPTR> {
@@ -1153,8 +1154,8 @@ def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
   [(global_store (v4i32 R600_Reg128:$rw_gpr), R600_TReg32_X:$index_gpr)]
 >;
 
-class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>
-    : InstR600ISA <outs, (ins MEMxi:$ptr), "VTX_READ_eg $dst, $ptr", pattern> {
+class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
+    : InstR600ISA <outs, (ins MEMxi:$ptr), name#" $dst, $ptr", pattern> {
 
   // Operands
   bits<7> DST_GPR;
@@ -1236,7 +1237,8 @@ class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>
 }
 
 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
-    : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
+    : VTX_READ_eg <"VTX_READ_8", buffer_id, (outs R600_TReg32_X:$dst),
+                   pattern> {
 
   let MEGA_FETCH_COUNT = 1;
   let DST_SEL_X = 0;
@@ -1247,7 +1249,8 @@ class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
 }
 
 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
-    : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
+    : VTX_READ_eg <"VTX_READ_32", buffer_id, (outs R600_TReg32_X:$dst),
+                   pattern> {
 
   let MEGA_FETCH_COUNT = 4;
   let DST_SEL_X        = 0;
@@ -1267,7 +1270,8 @@ class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
 }
 
 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern>
-    : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> {
+    : VTX_READ_eg <"VTX_READ_128", buffer_id, (outs R600_Reg128:$dst),
+                   pattern> {
 
   let MEGA_FETCH_COUNT = 16;
   let DST_SEL_X        =  0;
diff --git a/test/CodeGen/R600/load.constant_addrspace.f32.ll b/test/CodeGen/R600/load.constant_addrspace.f32.ll
index f5dc9db..9362728 100644
--- a/test/CodeGen/R600/load.constant_addrspace.f32.ll
+++ b/test/CodeGen/R600/load.constant_addrspace.f32.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: VTX_READ_eg T{{[0-9]+\.X, T[0-9]+\.X}}
+;CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}}
 
 define void @test(float addrspace(1)* %out, float addrspace(2)* %in) {
   %1 = load float addrspace(2)* %in
diff --git a/test/CodeGen/R600/load.i8.ll b/test/CodeGen/R600/load.i8.ll
index 4dfa541..b070dcd 100644
--- a/test/CodeGen/R600/load.i8.ll
+++ b/test/CodeGen/R600/load.i8.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: VTX_READ_eg T{{[0-9]+\.X, T[0-9]+\.X}}
+;CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
 
 define void @test(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
   %1 = load i8 addrspace(1)* %in
-- 
1.7.11.4