[Mesa-dev] [PATCH 6/6] AMDGPU: Remove unecessary VREG alignment.

[Christian König]

Unlike SGPRs VGPRs doesn't need to be aligned.

Signed-off-by: Christian König <deathsimple at vodafone.de>
---
 lib/Target/AMDGPU/SIRegisterInfo.td |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/lib/Target/AMDGPU/SIRegisterInfo.td b/lib/Target/AMDGPU/SIRegisterInfo.td
index e52311a..c3f1361 100644
--- a/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -105,15 +105,15 @@ def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
 
 // VGPR 64-bit registers
 def VGPR_64 : RegisterTuples<[low, high],
-                             [(add (decimate VGPR_32, 2)),
-                              (add (decimate (rotl VGPR_32, 1), 2))]>;
+                             [(add VGPR_32),
+                              (add (rotl VGPR_32, 1))]>;
 
 // VGPR 128-bit registers
 def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w],
-                              [(add (decimate VGPR_32, 4)),
-                               (add (decimate (rotl VGPR_32, 1), 4)),
-                               (add (decimate (rotl VGPR_32, 2), 4)),
-                               (add (decimate (rotl VGPR_32, 3), 4))]>;
+                              [(add VGPR_32),
+                               (add (rotl VGPR_32, 1)),
+                               (add (rotl VGPR_32, 2)),
+                               (add (rotl VGPR_32, 3))]>;
 
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
-- 
1.7.9.5