[Mesa-dev] [RFC PATCH 14/26] i965: add support for sample mask on Gen6+

[Chris Forbes]

Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
---
 src/mesa/drivers/dri/i965/brw_context.h            |  2 +-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp           |  2 +-
 src/mesa/drivers/dri/i965/gen6_multisample_state.c | 19 +++++++++++++------
 src/mesa/drivers/dri/i965/gen7_blorp.cpp           |  2 +-
 4 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index eba9eb5..25b82c4 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1228,7 +1228,7 @@ gen6_emit_3dstate_multisample(struct brw_context *brw,
 void
 gen6_emit_3dstate_sample_mask(struct brw_context *brw,
                               unsigned num_samples, float coverage,
-                              bool coverage_invert);
+                              bool coverage_invert, unsigned sample_mask);
 
 /* gen7_urb.c */
 void
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 13dbd30..2dab3ec 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1021,7 +1021,7 @@ gen6_blorp_exec(struct intel_context *intel,
    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
    gen6_blorp_emit_batch_head(brw, params);
    gen6_emit_3dstate_multisample(brw, params->num_samples);
-   gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false);
+   gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
    gen6_blorp_emit_state_base_address(brw, params);
    gen6_blorp_emit_vertices(brw, params);
    gen6_blorp_emit_urb_config(brw, params);
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index 64ac292..844aad1 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -116,7 +116,7 @@ gen6_emit_3dstate_multisample(struct brw_context *brw,
 void
 gen6_emit_3dstate_sample_mask(struct brw_context *brw,
                               unsigned num_samples, float coverage,
-                              bool coverage_invert)
+                              bool coverage_invert, unsigned sample_mask)
 {
    struct intel_context *intel = &brw->intel;
 
@@ -127,7 +127,7 @@ gen6_emit_3dstate_sample_mask(struct brw_context *brw,
       uint32_t coverage_bits = (1 << coverage_int) - 1;
       if (coverage_invert)
          coverage_bits ^= (1 << num_samples) - 1;
-      OUT_BATCH(coverage_bits);
+      OUT_BATCH(coverage_bits & sample_mask);
    } else {
       OUT_BATCH(1);
    }
@@ -141,21 +141,28 @@ static void upload_multisample_state(struct brw_context *brw)
    struct gl_context *ctx = &intel->ctx;
    float coverage = 1.0;
    float coverage_invert = false;
+   unsigned sample_mask = ~0u;
 
    /* _NEW_BUFFERS */
    unsigned num_samples = ctx->DrawBuffer->Visual.samples;
 
    /* _NEW_MULTISAMPLE */
-   if (ctx->Multisample._Enabled && ctx->Multisample.SampleCoverage) {
-      coverage = ctx->Multisample.SampleCoverageValue;
-      coverage_invert = ctx->Multisample.SampleCoverageInvert;
+   if (ctx->Multisample._Enabled) {
+      if (ctx->Multisample.SampleCoverage) {
+         coverage = ctx->Multisample.SampleCoverageValue;
+         coverage_invert = ctx->Multisample.SampleCoverageInvert;
+      }
+      if (ctx->Multisample.SampleMask) {
+         sample_mask = ctx->Multisample.SampleMaskValue;
+      }
    }
 
    /* 3DSTATE_MULTISAMPLE is nonpipelined. */
    intel_emit_post_sync_nonzero_flush(intel);
 
    gen6_emit_3dstate_multisample(brw, num_samples);
-   gen6_emit_3dstate_sample_mask(brw, num_samples, coverage, coverage_invert);
+   gen6_emit_3dstate_sample_mask(brw, num_samples, coverage,
+         coverage_invert, sample_mask);
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 3175273..0144b22 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -746,7 +746,7 @@ gen7_blorp_exec(struct intel_context *intel,
    gen6_blorp_emit_batch_head(brw, params);
    gen7_allocate_push_constants(brw);
    gen6_emit_3dstate_multisample(brw, params->num_samples);
-   gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false);
+   gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u);
    gen6_blorp_emit_state_base_address(brw, params);
    gen6_blorp_emit_vertices(brw, params);
    gen7_blorp_emit_urb_config(brw, params);
-- 
1.8.0.3