No subject

Tue Feb 7 00:14:52 PST 2012

+ =A0 =A0* BSpec, Volume 2a &quot;3D Pipeline Overview&quot;, Section 1.7.1=
 3DSTATE_URB_VS: 
+ =A0 =A0* =A0 =A0 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must =
also be 
+ =A0 =A0* =A0 =A0 programmed in order for the programming of this state to=
 be 
+ =A0 =A0* =A0 =A0 valid. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0/* The minimum valid value is 32. See 3DSTATE_URB_VS, 
+ =A0 =A0 =A0 * Dword 1.15:0 &quot;VS Number of URB Entries&quot;. 
+ =A0 =A0 =A0 */ 
+ =A0 =A0 =A0int num_vs_entries =3D 32; 
+ 
+ =A0 =A0 =A0BEGIN_BATCH(2); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_URB_VS &lt;&lt; 16 | (2 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(1 &lt;&lt; GEN7_URB_ENTRY_SIZE_SHIFT | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00 &lt;&lt; GEN7_URB_STARTING_ADDRESS_SHIFT=
 | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0num_vs_entries); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ 
+ =A0 =A0 =A0BEGIN_BATCH(2); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_URB_GS &lt;&lt; 16 | (2 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ 
+ =A0 =A0 =A0BEGIN_BATCH(2); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_URB_HS &lt;&lt; 16 | (2 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ 
+ =A0 =A0 =A0BEGIN_BATCH(2); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_URB_DS &lt;&lt; 16 | (2 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS 
+ =A0 =A0* 
+ =A0 =A0* The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBas=
eAddress. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0uint32_t depthstencil_offset; 
+ =A0 =A0 =A0gen6_hiz_emit_depth_stencil_state(brw, op, &amp;depthstencil_o=
ffset); 
+ 
+ =A0 =A0 =A0BEGIN_BATCH(2); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS &lt;&lt; 16 | =
(2 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(depthstencil_offset | 1); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_VS 
+ =A0 =A0* 
+ =A0 =A0* Disable vertex shader. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(6); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_VS &lt;&lt; 16 | (6 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_HS 
+ =A0 =A0* 
+ =A0 =A0* Disable the hull shader. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(7); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_HS &lt;&lt; 16 | (7 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_TE 
+ =A0 =A0* 
+ =A0 =A0* Disable the tesselation engine. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(4); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_TE &lt;&lt; 16 | (4 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_DS 
+ =A0 =A0* 
+ =A0 =A0* Disable the domain shader. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(6); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_DS &lt;&lt; 16 | (6)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_GS 
+ =A0 =A0* 
+ =A0 =A0* Disable the geometry shader. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(7); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_GS &lt;&lt; 16 | (7 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_STREAMOUT 
+ =A0 =A0* 
+ =A0 =A0* Disable streamout. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(3); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_STREAMOUT &lt;&lt; 16 | (3 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_CLIP 
+ =A0 =A0* 
+ =A0 =A0* Disable the clipper. 
+ =A0 =A0* 
+ =A0 =A0* The HiZ op emits a rectangle primitive, which requires clipping =
to 
+ =A0 =A0* be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part =
1 
+ =A0 =A0* Section 1.3 &quot;3D Primitives Overview&quot;: 
+ =A0 =A0* =A0 =A0RECTLIST: 
+ =A0 =A0* =A0 =A0Either the CLIP unit should be DISABLED, or the CLIP unit=
&#39;s Clip 
+ =A0 =A0* =A0 =A0Mode should be set to a value other than CLIPMODE_NORMAL.=
 
+ =A0 =A0* 
+ =A0 =A0* Also disable perspective divide. This doesn&#39;t change the cli=
pper&#39;s 
+ =A0 =A0* output, but does spare a few electrons. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(4); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_CLIP &lt;&lt; 16 | (4 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_SF 
+ =A0 =A0* 
+ =A0 =A0* Disable ViewportTransformEnable (dw1.1) 
+ =A0 =A0* 
+ =A0 =A0* From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, &quot;3=
D 
+ =A0 =A0* Primitives Overview&quot;: 
+ =A0 =A0* =A0 =A0 RECTLIST: Viewport Mapping must be DISABLED (as is typic=
al with the 
+ =A0 =A0* =A0 =A0 use of screen- space coordinates). 
+ =A0 =A0* 
+ =A0 =A0* A solid rectangle must be rendered, so set FrontFaceFillMode (dw=
1.6:5) 
+ =A0 =A0* and BackFaceFillMode (dw1.4:3) to SOLID(0). 
+ =A0 =A0* 
+ =A0 =A0* From the Sandy Bridge PRM, Volume 2, Part 1, Section 
+ =A0 =A0* 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode: 
+ =A0 =A0* =A0 =A0 SOLID: Any triangle or rectangle object found to be fron=
t-facing 
+ =A0 =A0* =A0 =A0 is rendered as a solid object. This setting is required =
when 
+ =A0 =A0* =A0 =A0 (rendering rectangle (RECTLIST) objects. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0uint32_t format; 
+ =A0 =A0 =A0switch (mt-&gt;format) { 
+ =A0 =A0 =A0case MESA_FORMAT_Z16: =A0 =A0 =A0 format =3D BRW_DEPTHFORMAT_D=
16_UNORM; break; 
+ =A0 =A0 =A0case MESA_FORMAT_Z32_FLOAT: format =3D BRW_DEPTHFORMAT_D32_FLO=
AT; break; 
+ =A0 =A0 =A0case MESA_FORMAT_X8_Z24: =A0 =A0format =3D BRW_DEPTHFORMAT_D24=
_UNORM_X8_UINT; break; 
+ =A0 =A0 =A0default: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0assert(0); bre=
ak; 
+ =A0 =A0 =A0} 
+ 
+ =A0 =A0 =A0BEGIN_BATCH(7); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_SF &lt;&lt; 16 | (7 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(format &lt;&lt; GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_=
SHIFT); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_SBE */ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(14); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_SBE &lt;&lt; 16 | (14 - 2)); 
+ =A0 =A0 =A0OUT_BATCH((1 - 1) &lt;&lt; GEN7_SBE_NUM_OUTPUTS_SHIFT | /* onl=
y position */ 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A01 &lt;&lt; GEN7_SBE_URB_ENTRY_READ_LENGTH_=
SHIFT | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00 &lt;&lt; GEN7_SBE_URB_ENTRY_READ_OFFSET_=
SHIFT); 
+ =A0 =A0 =A0for (int i =3D 0; i &lt; 12; ++i) 
+ =A0 =A0 =A0 =A0 OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_WM 
+ =A0 =A0* 
+ =A0 =A0* Disable PS thread dispatch (dw1.29) and enable the HiZ op. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0uint32_t dw1 =3D 0; 
+ 
+ =A0 =A0 =A0switch (op) { 
+ =A0 =A0 =A0case GEN6_HIZ_OP_DEPTH_CLEAR: 
+ =A0 =A0 =A0 =A0 assert(!&quot;not implemented&quot;); 
+ =A0 =A0 =A0 =A0 dw1 |=3D GEN7_WM_DEPTH_CLEAR; 
+ =A0 =A0 =A0 =A0 break; 
+ =A0 =A0 =A0case GEN6_HIZ_OP_DEPTH_RESOLVE: 
+ =A0 =A0 =A0 =A0 dw1 |=3D GEN7_WM_DEPTH_RESOLVE; 
+ =A0 =A0 =A0 =A0 break; 
+ =A0 =A0 =A0case GEN6_HIZ_OP_HIZ_RESOLVE: 
+ =A0 =A0 =A0 =A0 dw1 |=3D GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE; 
+ =A0 =A0 =A0 =A0 break; 
+ =A0 =A0 =A0default: 
+ =A0 =A0 =A0 =A0 assert(0); 
+ =A0 =A0 =A0 =A0 break; 
+ =A0 =A0 =A0} 
+ 
+ =A0 =A0 =A0BEGIN_BATCH(3); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_WM &lt;&lt; 16 | (3 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(dw1); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_PS 
+ =A0 =A0* 
+ =A0 =A0* Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. D=
espite 
+ =A0 =A0* that, thread dispatch info must still be specified. 
+ =A0 =A0* =A0 =A0 - Maximum Number of Threads (dw4.24:31) must be nonzero,=
 as the BSpec 
+ =A0 =A0* =A0 =A0 =A0 states that the valid range for this field is [0x3, =
0x2f]. 
+ =A0 =A0* =A0 =A0 - A dispatch mode must be given; that is, at least one o=
f the 
+ =A0 =A0* =A0 =A0 =A0 &quot;N Pixel Dispatch Enable&quot; (N=3D8,16,32) fi=
elds must be set. This was 
+ =A0 =A0* =A0 =A0 =A0 discovered through simulator error messages. 
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(8); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_PS &lt;&lt; 16 | (8 - 2)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH((brw-&gt;max_wm_threads - 1) &lt;&lt; GEN7_PS_MAX_TH=
READS_SHIFT); 
+ =A0 =A0 =A0OUT_BATCH(GEN7_PS_32_DISPATCH_ENABLE); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_DEPTH_BUFFER */ 
+ =A0 { 
+ =A0 =A0 =A0uint32_t width =3D mt-&gt;level[level].width; 
+ =A0 =A0 =A0uint32_t height =3D mt-&gt;level[level].height; 
+ 
+ =A0 =A0 =A0uint32_t tile_x; 
+ =A0 =A0 =A0uint32_t tile_y; 
+ =A0 =A0 =A0uint32_t offset; 
+ =A0 =A0 =A0{ 
+ =A0 =A0 =A0 =A0 /* Construct a dummy renderbuffer just to extract tile of=
fsets. */ 
+ =A0 =A0 =A0 =A0 struct intel_renderbuffer rb; 
+ =A0 =A0 =A0 =A0 <a href=3D"http://rb.mt" target=3D"_blank">rb.mt</a> =3D =
mt; 
+ =A0 =A0 =A0 =A0 rb.mt_level =3D level; 
+ =A0 =A0 =A0 =A0 rb.mt_layer =3D layer; 
+ =A0 =A0 =A0 =A0 intel_renderbuffer_set_draw_offset(&amp;rb); 
+ =A0 =A0 =A0 =A0 offset =3D intel_renderbuffer_tile_offsets(&amp;rb, &amp;=
tile_x, &amp;tile_y); 
+ =A0 =A0 =A0} 
+ 
+ =A0 =A0 =A0uint32_t format; 
+ =A0 =A0 =A0switch (mt-&gt;format) { 
+ =A0 =A0 =A0case MESA_FORMAT_Z16: =A0 =A0 =A0 format =3D BRW_DEPTHFORMAT_D=
16_UNORM; break; 
+ =A0 =A0 =A0case MESA_FORMAT_Z32_FLOAT: format =3D BRW_DEPTHFORMAT_D32_FLO=
AT; break; 
+ =A0 =A0 =A0case MESA_FORMAT_X8_Z24: =A0 =A0format =3D BRW_DEPTHFORMAT_D24=
_UNORM_X8_UINT; break; 
+ =A0 =A0 =A0default: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0assert(0); bre=
ak; 
+ =A0 =A0 =A0} 
+ 
+ =A0 =A0 =A0intel_emit_depth_stall_flushes(intel); 
+ 
+ =A0 =A0 =A0BEGIN_BATCH(7); 
+ =A0 =A0 =A0OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER &lt;&lt; 16 | (7 - 2));<br=
>
+ =A0 =A0 =A0OUT_BATCH(((mt-&gt;region-&gt;pitch * mt-&gt;region-&gt;cpp) -=
 1) | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0format &lt;&lt; 18 | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A01 &lt;&lt; 22 | /* hiz enable */ 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A01 &lt;&lt; 28 | /* depth write */ 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0BRW_SURFACE_2D &lt;&lt; 29); 
+ =A0 =A0 =A0OUT_RELOC(mt-&gt;region-&gt;bo, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RE=
NDER, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0offset); 
+ =A0 =A0 =A0OUT_BATCH((width + tile_x - 1) &lt;&lt; 4 | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(height + tile_y - 1) &lt;&lt; 18); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(tile_x | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tile_y &lt;&lt; 16); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_HIER_DEPTH_BUFFER */ 
+ =A0 { 
+ =A0 =A0 =A0struct intel_region *hiz_region =3D mt-&gt;hiz_mt-&gt;region;<=
br>
+ 
+ =A0 =A0 =A0BEGIN_BATCH(3); 
+ =A0 =A0 =A0OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER &lt;&lt; 16) | (3 - =
2)); 
+ =A0 =A0 =A0OUT_BATCH(hiz_region-&gt;pitch * hiz_region-&gt;cpp - 1); 
+ =A0 =A0 =A0OUT_RELOC(hiz_region-&gt;bo, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RE=
NDER, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A00); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_STENCIL_BUFFER */ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(3); 
+ =A0 =A0 =A0OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER &lt;&lt; 16) | (3 - 2))=
; 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_CLEAR_PARAMS 
+ =A0 =A0* 
+ =A0 =A0* From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2 
+ =A0 =A0* 3DSTATE_CLEAR_PARAMS: 
+ =A0 =A0* =A0 =A0[DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed i=
n the along 
+ =A0 =A0* =A0 =A0with the other Depth/Stencil state commands(i.e. =A03DSTA=
TE_DEPTH_BUFFER, 
+ =A0 =A0* =A0 =A03DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).<br=
>
+ =A0 =A0*/ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(3); 
+ =A0 =A0 =A0OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS &lt;&lt; 16 | (3 - 2));<br=
>
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DSTATE_DRAWING_RECTANGLE */ 
+ =A0 { 
+ =A0 =A0 =A0BEGIN_BATCH(4); 
+ =A0 =A0 =A0OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE &lt;&lt; 16 | (4 - 2));<b=
r>
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0OUT_BATCH(((mt-&gt;level[level].width - 1) &amp; 0xffff) | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((mt-&gt;level[level].height - 1) &lt;&lt;=
 16)); 
+ =A0 =A0 =A0OUT_BATCH(0); 
+ =A0 =A0 =A0ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* 3DPRIMITIVE */ 
+ =A0 { 
+ =A0 =A0 BEGIN_BATCH(7); 
+ =A0 =A0 OUT_BATCH(CMD_3D_PRIM &lt;&lt; 16 | (7 - 2)); 
+ =A0 =A0 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL | 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 _3DPRIM_RECTLIST); 
+ =A0 =A0 OUT_BATCH(3); /* vertex count per instance */ 
+ =A0 =A0 OUT_BATCH(0); 
+ =A0 =A0 OUT_BATCH(1); /* instance count */ 
+ =A0 =A0 OUT_BATCH(0); 
+ =A0 =A0 OUT_BATCH(0); 
+ =A0 =A0 ADVANCE_BATCH(); 
+ =A0 } 
+ 
+ =A0 /* See comments above at first invocation of intel_flush() in 
+ =A0 =A0* gen6_hiz_emit_batch_head(). 
+ =A0 =A0*/ 
+ =A0 intel_flush(ctx); 
+ 
+ =A0 /* Be safe. */ 
+ =A0 brw-&gt;state.dirty.brw =3D ~0; 
+ =A0 brw-&gt;state.dirty.cache =3D ~0; 
+} 
+ 
+/** \copydoc gen6_resolve_hiz_slice() */ 
+void 
+gen7_resolve_hiz_slice(struct intel_context *intel, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct intel_mipmap_tree *mt,=
 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t level, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t layer) 
+{ 
+ =A0 gen7_hiz_exec(intel, mt, level, layer, GEN6_HIZ_OP_HIZ_RESOLVE); 
+} 
+ 
+/** \copydoc gen6_resolve_depth_slice() */ 
+void 
+gen7_resolve_depth_slice(struct intel_context *intel, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct intel_mipmap_tree =
*mt, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t level, 
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t layer) 
+{ 
+ =A0 gen7_hiz_exec(intel, mt, level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE);<br=
>
+}

diff --git a/src/mesa/drivers/dri/i965/gen7_hiz.h b/src/mesa/drivers/dri/i9=
65/gen7_hiz.h<br>
new file mode 100644<br>
index 0000000..b89ffb0<br>
--- /dev/null<br>
+++ b/src/mesa/drivers/dri/i965/gen7_hiz.h<br>
@@ -0,0 +1,43 @@<br>
+/*<br>
+ * Copyright =A9 2011 Intel Corporation<br>
+ *<br>
+ * Permission is hereby granted, free of charge, to any person obtaining a=
<br>
+ * copy of this software and associated documentation files (the &quot;Sof=
tware&quot;),<br>
+ * to deal in the Software without restriction, including without limitati=
on<br>
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense=
,<br>
+ * and/or sell copies of the Software, and to permit persons to whom the<b=
r>
+ * Software is furnished to do so, subject to the following conditions:<br=
>
+ *<br>
+ * The above copyright notice and this permission notice (including the ne=
xt<br>
+ * paragraph) shall be included in all copies or substantial portions of t=
he<br>
+ * Software.<br>
+ *<br>
+ * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIN=
D, EXPRESS OR<br>
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY=
,<br>
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. =A0IN NO EVENT SH=
ALL<br>
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT=
HER<br>
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING=
<br>
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEA=
LINGS<br>
+ * IN THE SOFTWARE.<br>
+ */<br>
+<br>
+#pragma once<br>
+<br>
+#include &lt;stdint.h&gt;<br>
+<br>
+struct intel_context;<br>
+struct intel_mipmap_tree;<br>
+<br>
+/** \copydoc gen6_resolve_hiz_slice() */<br>
+void<br>
+gen7_resolve_hiz_slice(struct intel_context *intel,<br>
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct intel_mipmap_tree *mt,=
<br>
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t level,<br>
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t layer);<br>
+<br>
+/** \copydoc gen6_resolve_depth_slice() */<br>
+void<br>
+gen7_resolve_depth_slice(struct intel_context *intel,<br>
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct intel_mipmap_tree =
*mt,<br>
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t level,<br>
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 uint32_t layer);<br>
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/d=
ri/i965/gen7_sf_state.c<br>
index da7ef81..b215af2 100644<br>
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c<br>
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c<br>
@@ -149,8 +149,7 @@ const struct brw_tracked_state gen7_sbe_state =3D {<br>
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_NEW_PROGRAM |<br>
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_NEW_TRANSFORM),<br>
 =A0 =A0 =A0 .brw =A0 =3D (BRW_NEW_CONTEXT |<br>
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 BRW_NEW_FRAGMENT_PROGRAM |<br>
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 BRW_NEW_HIZ),<br>
+ =A0 =A0 =A0 =A0 =A0 =A0 =A0 BRW_NEW_FRAGMENT_PROGRAM),<br>
 =A0 =A0 =A0 .cache =3D CACHE_NEW_VS_PROG<br>
 =A0 =A0},<br>
 =A0 =A0.emit =3D upload_sbe_state,<br>
@@ -166,17 +165,8 @@ upload_sf_state(struct brw_context *brw)<br>
 =A0 =A0/* _NEW_BUFFERS */<br>
 =A0 =A0bool render_to_fbo =3D brw-&gt;intel.ctx.DrawBuffer-&gt;Name !=3D 0=
;<br>
<br>
- =A0 dw1 =3D GEN6_SF_STATISTICS_ENABLE;<br>
-<br>
- =A0 /* Enable viewport transform only if no HiZ operation is progress<br>
- =A0 =A0*<br>
- =A0 =A0* From page 11 of the SandyBridge PRM, Volume 2, Part 1, Section 1=
.3, &quot;3D<br>
- =A0 =A0* Primitives Overview&quot;:<br>
- =A0 =A0* =A0 =A0 RECTLIST: Viewport Mapping must be DISABLED (as is typic=
al with the<br>
- =A0 =A0* =A0 =A0 use of screen- space coordinates).<br>
- =A0 =A0*/<br>
- =A0 if (!brw-&gt;hiz.op)<br>
- =A0 =A0 =A0dw1 |=3D GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;<br>
+ =A0 dw1 =3D GEN6_SF_STATISTICS_ENABLE |<br>
+ =A0 =A0 =A0 =A0 GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;<br>
<br>
 =A0 =A0/* _NEW_BUFFERS */<br>
 =A0 =A0dw1 |=3D (brw_depthbuffer_format(brw) &lt;&lt; GEN7_SF_DEPTH_BUFFER=
_SURFACE_FORMAT_SHIFT);<br>
@@ -310,8 +300,7 @@ const struct brw_tracked_state gen7_sf_state =3D {<br>
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_NEW_SCISSOR |<br>
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_NEW_BUFFERS |<br>
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_NEW_POINT),<br>
- =A0 =A0 =A0.brw =A0 =3D (BRW_NEW_CONTEXT |<br>
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 BRW_NEW_HIZ),<br>
+ =A0 =A0 =A0.brw =A0 =3D BRW_NEW_CONTEXT,<br>
 =A0 =A0 =A0 .cache =3D CACHE_NEW_VS_PROG<br>
 =A0 =A0},<br>
 =A0 =A0.emit =3D upload_sf_state,<br>
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/d=
ri/i965/gen7_wm_state.c<br>
index 32222f9..870590f 100644<br>
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c<br>
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c<br>
@@ -49,23 +49,6 @@ upload_wm_state(struct brw_context *brw)<br>
 =A0 =A0dw1 |=3D GEN7_WM_LINE_AA_WIDTH_1_0;<br>
 =A0 =A0dw1 |=3D GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;<br>
<br>
- =A0 switch (brw-&gt;hiz.op) {<br>
- =A0 case BRW_HIZ_OP_NONE:<br>
- =A0 =A0 =A0break;<br>
- =A0 case BRW_HIZ_OP_DEPTH_CLEAR:<br>
- =A0 =A0 =A0dw1 |=3D GEN7_WM_DEPTH_CLEAR;<br>
- =A0 =A0 =A0break;<br>
- =A0 case BRW_HIZ_OP_DEPTH_RESOLVE:<br>
- =A0 =A0 =A0dw1 |=3D GEN7_WM_DEPTH_RESOLVE;<br>
- =A0 =A0 =A0break;<br>
- =A0 case BRW_HIZ_OP_HIZ_RESOLVE:<br>
- =A0 =A0 =A0dw1 |=3D GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;<br>
- =A0 =A0 =A0break;<br>
- =A0 default:<br>
- =A0 =A0 =A0assert(0);<br>
- =A0 =A0 =A0break;<br>
- =A0 }<br>
-<br>
 =A0 =A0/* _NEW_LINE */<br>
 =A0 =A0if (ctx-&gt;Line.StippleFlag)<br>
 =A0 =A0 =A0 dw1 |=3D GEN7_WM_LINE_STIPPLE_ENABLE;<br>
@@ -106,7 +89,6 @@ const struct brw_tracked_state gen7_wm_state =3D {<br>
 =A0 =A0 =A0 .mesa =A0=3D (_NEW_LINE | _NEW_LIGHT | _NEW_POLYGON |<br>
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_NEW_COLOR | _NEW_BUFFERS),<br>
 =A0 =A0 =A0 .brw =A0 =3D (BRW_NEW_FRAGMENT_PROGRAM |<br>
- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0BRW_NEW_HIZ |<br>
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0BRW_NEW_BATCH),<br>
 =A0 =A0 =A0 .cache =3D 0,<br>
 =A0 =A0},<br>
diff --git a/src/mesa/drivers/dri/i965/junk b/src/mesa/drivers/dri/i965/jun=
k<br>
new file mode 100644<br>
index 0000000..e69de29<br>
<span class=3D"HOEnZb"><font color=3D"#888888">--<br>
1.7.7.5<br>
<br>
</font></span></blockquote></div><br>Just to be on record about something w=
e&#39;ve discussed in person:=A0 I&#39;m not terribly comfortable with the =
code duplication involved in having these new Hi-Z functions emit a lot of =
the same command packets that are normally emitted through state atoms.=A0 =
My worry is that if in the future we discover some hardware workaround that=
 is needed in a state atom, we won&#39;t remember to update these Hi-Z func=
tions.=A0 I would prefer if we could look for ways to share code between th=
e state atoms and the Hi-Z functions.=A0 However, considering how close we =
are to the Mesa 8.0 release, I am happy doing that as a post-8.0 activity.<=
br>
<br>Acked-by: Paul Berry &lt;<a href=3D"mailto:stereotype441 at gmail.com">ste=
reotype441 at gmail.com</a>&gt;<br>

--0015175cfc866d186004b853e513--
