[Mesa-dev] [PATCH 1/6] r600g: turn init_config into a command buffer for starting a CS
Alex Deucher
alexdeucher at gmail.com
Fri Feb 17 07:44:40 PST 2012
On Thu, Feb 16, 2012 at 4:04 PM, Marek Olšák <maraeo at gmail.com> wrote:
> This is the first pure command buffer. It contains CS initialization
> packets and emits invariant state (i.e. the registers which never or rarely
> change).
>
> The affected registers are removed from *_hw_context.c, so that both ways
> of emitting commands can co-exist.
> ---
> src/gallium/drivers/r600/evergreen_hw_context.c | 141 +--------
> src/gallium/drivers/r600/evergreen_state.c | 406 ++++++++++++-----------
> src/gallium/drivers/r600/evergreend.h | 1 -
> src/gallium/drivers/r600/r600_hw_context.c | 63 +----
> src/gallium/drivers/r600/r600_hw_context_priv.h | 1 -
> src/gallium/drivers/r600/r600_pipe.c | 5 +-
> src/gallium/drivers/r600/r600_pipe.h | 67 ++++-
> src/gallium/drivers/r600/r600_state.c | 142 ++++----
> src/gallium/drivers/r600/r600_state_common.c | 24 ++
> src/gallium/drivers/r600/r600d.h | 3 -
> 10 files changed, 374 insertions(+), 479 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
> index b24f168..00fdade 100644
> --- a/src/gallium/drivers/r600/evergreen_hw_context.c
> +++ b/src/gallium/drivers/r600/evergreen_hw_context.c
> @@ -34,33 +34,11 @@
>
> static const struct r600_reg evergreen_config_reg_list[] = {
> {R_008958_VGT_PRIMITIVE_TYPE, 0},
> - {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C0C_SQ_GPR_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C18_SQ_THREAD_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C20_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C24_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C28_SQ_STACK_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008E2C_SQ_LDS_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> };
>
>
> static const struct r600_reg cayman_config_reg_list[] = {
> {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
> - {R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> {R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> {R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> };
> @@ -125,38 +103,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
> {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
> {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
> {R_028350_SX_MISC, 0, 0},
> - {R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
> - {R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
> - {R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
> - {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
> - {R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
> - {R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
> - {R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
> - {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
> - {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
> - {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
> - {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
> - {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
> - {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
> - {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
> - {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
> - {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
> - {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
> - {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
> - {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
> - {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
> - {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
> - {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
> - {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
> - {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
> - {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
> - {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
> - {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
> - {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
> - {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
> - {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
> - {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
> - {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
> {GROUP_FORCE_NEW_BLOCK, 0, 0},
> {R_028400_VGT_MAX_VTX_INDX, 0, 0},
> {R_028404_VGT_MIN_VTX_INDX, 0, 0},
> @@ -273,7 +219,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
> {R_028818_PA_CL_VTE_CNTL, 0, 0},
> {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
> {R_028820_PA_CL_NANINF_CNTL, 0, 0},
> - {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0},
> {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0},
> {R_028844_SQ_PGM_RESOURCES_PS, 0, 0},
> {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0},
> @@ -284,16 +229,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
> {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
> {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0},
> {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
> - {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
> - {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
> - {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
> - {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
> - {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
> - {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
> - {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0},
> - {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
> - {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
> - {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
> {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
> {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
> {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
> @@ -302,23 +237,7 @@ static const struct r600_reg evergreen_context_reg_list[] = {
> {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
> {R_028A08_PA_SU_LINE_CNTL, 0, 0},
> {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
> - {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0},
> - {R_028A14_VGT_HOS_CNTL, 0, 0},
> - {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0},
> - {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0},
> - {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0},
> - {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0},
> - {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0},
> - {R_028A2C_VGT_GROUP_DECR, 0, 0},
> - {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0},
> - {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0},
> - {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0},
> - {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0},
> - {R_028A40_VGT_GS_MODE, 0, 0},
> {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
> - {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0},
> - {R_028AB4_VGT_REUSE_OFF, 0, 0},
> - {R_028AB8_VGT_VTX_CNT_EN, 0, 0},
> {R_028ABC_DB_HTILE_SURFACE, 0, 0},
> {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0},
> {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0},
> @@ -331,8 +250,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
> {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
> {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
> {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
> - {R_028B94_VGT_STRMOUT_CONFIG, 0, 0},
> - {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0},
> {R_028C00_PA_SC_LINE_CNTL, 0, 0},
> {R_028C04_PA_SC_AA_CONFIG, 0, 0},
> {R_028C08_PA_SU_VTX_CNTL, 0, 0},
> @@ -495,38 +412,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
> {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0},
> {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0},
> {R_028350_SX_MISC, 0, 0},
> - {R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
> - {R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
> - {R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
> - {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0},
> - {R_028390_SQ_VTX_SEMANTIC_4, 0, 0},
> - {R_028394_SQ_VTX_SEMANTIC_5, 0, 0},
> - {R_028398_SQ_VTX_SEMANTIC_6, 0, 0},
> - {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0},
> - {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0},
> - {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0},
> - {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0},
> - {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0},
> - {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0},
> - {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0},
> - {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0},
> - {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0},
> - {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0},
> - {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0},
> - {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0},
> - {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0},
> - {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0},
> - {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0},
> - {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0},
> - {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0},
> - {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0},
> - {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0},
> - {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0},
> - {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0},
> - {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0},
> - {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0},
> - {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0},
> - {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0},
> {GROUP_FORCE_NEW_BLOCK, 0, 0},
> {R_028400_VGT_MAX_VTX_INDX, 0, 0},
> {R_028404_VGT_MIN_VTX_INDX, 0, 0},
> @@ -633,7 +518,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
> {R_028798_CB_BLEND6_CONTROL, 0, 0},
> {R_02879C_CB_BLEND7_CONTROL, 0, 0},
> {R_028800_DB_DEPTH_CONTROL, 0, 0},
> - {CM_R_028804_DB_EQAA, 0, 0},
> {R_028808_CB_COLOR_CONTROL, 0, 0},
> {R_02880C_DB_SHADER_CONTROL, 0, 0},
> {R_028810_PA_CL_CLIP_CNTL, 0, 0},
> @@ -651,8 +535,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
> {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0},
> {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0},
> {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0},
> - {CM_R_0288E8_SQ_LDS_ALLOC, 0, 0},
> - {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0},
> {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0},
> {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0},
> {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
> @@ -671,24 +553,7 @@ static const struct r600_reg cayman_context_reg_list[] = {
> {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
> {R_028A08_PA_SU_LINE_CNTL, 0, 0},
> {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
> - {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0},
> - {R_028A14_VGT_HOS_CNTL, 0, 0},
> - {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0},
> - {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0},
> - {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0},
> - {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0},
> - {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0},
> - {R_028A2C_VGT_GROUP_DECR, 0, 0},
> - {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0},
> - {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0},
> - {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0},
> - {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0},
> - {R_028A40_VGT_GS_MODE, 0, 0},
> {R_028A48_PA_SC_MODE_CNTL_0, 0, 0},
> - {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0},
> - {CM_R_028AA8_IA_MULTI_VGT_PARAM, 0, 0},
> - {R_028AB4_VGT_REUSE_OFF, 0, 0},
> - {R_028AB8_VGT_VTX_CNT_EN, 0, 0},
> {R_028ABC_DB_HTILE_SURFACE, 0, 0},
> {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0},
> {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0},
> @@ -701,10 +566,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
> {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
> {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
> {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
> - {R_028B94_VGT_STRMOUT_CONFIG, 0, 0},
> - {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0},
> - {CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0, 0},
> - {CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0, 0},
> {CM_R_028BDC_PA_SC_LINE_CNTL, 0, 0},
> {CM_R_028BE0_PA_SC_AA_CONFIG, 0, 0},
> {CM_R_028BE4_PA_SU_VTX_CNTL, 0, 0},
> @@ -995,8 +856,8 @@ int evergreen_context_init(struct r600_context *ctx)
> goto out_err;
>
> ctx->cs = ctx->ws->cs_create(ctx->ws);
> + r600_emit_atom(ctx, &ctx->atom_start_cs.atom);
>
> - r600_init_cs(ctx);
> ctx->max_db = 8;
> return 0;
> out_err:
> diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
> index be193a2..905aef9 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -1803,91 +1803,100 @@ void evergreen_init_state_functions(struct r600_context *rctx)
> rctx->context.set_stream_output_targets = r600_set_so_targets;
> }
>
> -static void cayman_init_config(struct r600_context *rctx)
> +static void cayman_init_atom_start_cs(struct r600_context *rctx)
> {
> - struct r600_pipe_state *rstate = &rctx->config;
> - unsigned tmp;
> + struct r600_command_buffer *cb = &rctx->atom_start_cs;
>
> - tmp = 0x00000000;
> - tmp |= S_008C00_EXPORT_SRC_C(1);
> - r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
> + r600_init_command_buffer(cb, 256, EMIT_EARLY);
>
You need to emit the PKT3_CONTEXT_CONTROL sequence at the start of the
command buffer on cayman as well.
Alex
> + r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
> + r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
> /* always set the temp clauses */
> - r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63), NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
> - r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, NULL, 0);
> - r600_context_pipe_state_set(rctx, rstate);
> + r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
> +
> + r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
> + r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
> + r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
> +
> + r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
> +
> + r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
> +
> + r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
> + r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
> + r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
> + r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
> + r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
> + r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
> + r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
> + r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
> + r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
> + r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
> + r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
> + r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
> + r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
> + r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
> +
> + r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
> + r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
> + r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
> +
> + r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
> + r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
> + r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
> +
> + r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
> +
> + r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
> +
> + r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
> + r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
> + r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
> +
> + r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
> + r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
> + r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
> +
> + r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
> +
> + r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 32);
> + r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
> }
>
> -void evergreen_init_config(struct r600_context *rctx)
> +void evergreen_init_atom_start_cs(struct r600_context *rctx)
> {
> - struct r600_pipe_state *rstate = &rctx->config;
> + struct r600_command_buffer *cb = &rctx->atom_start_cs;
> int ps_prio;
> int vs_prio;
> int gs_prio;
> @@ -1915,13 +1924,19 @@ void evergreen_init_config(struct r600_context *rctx)
> enum radeon_family family;
> unsigned tmp;
>
> - family = rctx->family;
> -
> if (rctx->chip_class == CAYMAN) {
> - cayman_init_config(rctx);
> + cayman_init_atom_start_cs(rctx);
> return;
> }
> -
> +
> + r600_init_command_buffer(cb, 256, EMIT_EARLY);
> +
> + /* This must be first. */
> + r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
> + r600_store_value(cb, 0x80000000);
> + r600_store_value(cb, 0x80000000);
> +
> + family = rctx->family;
> ps_prio = 0;
> vs_prio = 1;
> gs_prio = 2;
> @@ -2145,7 +2160,7 @@ void evergreen_init_config(struct r600_context *rctx)
> break;
> }
>
> - tmp = 0x00000000;
> + tmp = 0;
> switch (family) {
> case CHIP_CEDAR:
> case CHIP_PALM:
> @@ -2165,150 +2180,145 @@ void evergreen_init_config(struct r600_context *rctx)
> tmp |= S_008C00_VS_PRIO(vs_prio);
> tmp |= S_008C00_GS_PRIO(gs_prio);
> tmp |= S_008C00_ES_PRIO(es_prio);
> - r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
>
> /* enable dynamic GPR resource management */
> if (rctx->screen->info.drm_minor >= 7) {
> + r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
> + r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
> /* always set temp clauses */
> - r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
> - S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
> + r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
> + r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
> + r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
> + r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
> + r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
> + r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
> S_028838_PS_GPRS(0x1e) |
> S_028838_VS_GPRS(0x1e) |
> S_028838_GS_GPRS(0x1e) |
> S_028838_ES_GPRS(0x1e) |
> S_028838_HS_GPRS(0x1e) |
> - S_028838_LS_GPRS(0x1e), NULL, 0); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
> + S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
> } else {
> - tmp = 0;
> - tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
> + r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
> + r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
> +
> + tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
> tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
> tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
> - r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
>
> - tmp = 0;
> - tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
> + tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
> tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
> - r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
>
> - tmp = 0;
> - tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
> + tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
> tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
> - r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
> }
>
> - tmp = 0;
> - tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
> + tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
> tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
> tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
> tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
> - r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, NULL, 0);
> + r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
> + r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
>
> - tmp = 0;
> - tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
> + tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
> tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
> - r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
>
> - tmp = 0;
> - tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
> + tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
> tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
> - r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
>
> - tmp = 0;
> - tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
> + tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
> tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
> - r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
>
> - tmp = 0;
> - tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
> + tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
> tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
> - r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, NULL, 0);
> -
> - tmp = 0;
> - tmp |= S_008E2C_NUM_PS_LDS(0x1000);
> - tmp |= S_008E2C_NUM_LS_LDS(0x1000);
> - r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), NULL, 0);
> -
> -#if 0
> - r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, NULL, 0);
> -#endif
> - r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
> -
> - r600_context_pipe_state_set(rctx, rstate);
> + r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
> +
> + r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
> + S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
> +
> + r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
> + r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
> +
> + r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
> +
> + r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
> + r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
> +
> + r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
> + r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
> + r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
> + r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
> +
> + r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
> + r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
> + r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
> + r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
> + r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
> + r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
> + r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
> + r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
> + r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
> + r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
> + r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
> + r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
> + r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
> + r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
> +
> + r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
> + r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
> + r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
> +
> + r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
> + r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
> + r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
> +
> + r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
> +
> + r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 32);
> + r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0);
> + r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_31 */
> }
>
> void evergreen_polygon_offset_update(struct r600_context *rctx)
> diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
> index d1dbd84..66b3d1f 100644
> --- a/src/gallium/drivers/r600/evergreend.h
> +++ b/src/gallium/drivers/r600/evergreend.h
> @@ -117,7 +117,6 @@
> #define PKT3_IT_OPCODE_C 0xFFFF00FF
> #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
> #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
> -#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate))
>
> /* Registers */
> #define R_0084FC_CP_STRMOUT_CNTL 0x000084FC
> diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
> index 1de345c..ef29ddf 100644
> --- a/src/gallium/drivers/r600/r600_hw_context.c
> +++ b/src/gallium/drivers/r600/r600_hw_context.c
> @@ -127,23 +127,6 @@ static inline void r600_context_ps_partial_flush(struct r600_context *ctx)
> ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
> }
>
> -void r600_init_cs(struct r600_context *ctx)
> -{
> - struct radeon_winsys_cs *cs = ctx->cs;
> -
> - /* R6xx requires this packet at the start of each command buffer */
> - if (ctx->family < CHIP_RV770) {
> - cs->buf[cs->cdw++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0);
> - cs->buf[cs->cdw++] = 0x00000000;
> - }
> - /* All asics require this one */
> - cs->buf[cs->cdw++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0);
> - cs->buf[cs->cdw++] = 0x80000000;
> - cs->buf[cs->cdw++] = 0x80000000;
> -
> - ctx->init_dwords = cs->cdw;
> -}
> -
> static void r600_init_block(struct r600_context *ctx,
> struct r600_block *block,
> const struct r600_reg *reg, int index, int nreg,
> @@ -262,17 +245,8 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
> /* R600/R700 configuration */
> static const struct r600_reg r600_config_reg_list[] = {
> {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
> - {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> - {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
> };
>
> static const struct r600_reg r600_ctl_const_list[] = {
> @@ -281,35 +255,7 @@ static const struct r600_reg r600_ctl_const_list[] = {
> };
>
> static const struct r600_reg r600_context_reg_list[] = {
> - {R_028350_SX_MISC, 0, 0},
> - {R_0286C8_SPI_THREAD_GROUPING, 0, 0},
> - {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0},
> - {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0},
> - {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0},
> - {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0},
> - {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0},
> - {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0},
> - {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0},
> - {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0},
> - {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0},
> - {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0},
> - {R_028A14_VGT_HOS_CNTL, 0, 0},
> - {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0},
> - {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0},
> - {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0},
> - {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0},
> - {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0},
> - {R_028A2C_VGT_GROUP_DECR, 0, 0},
> - {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0},
> - {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0},
> - {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0},
> - {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0},
> - {R_028A40_VGT_GS_MODE, 0, 0},
> {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
> - {R_028AB0_VGT_STRMOUT_EN, 0, 0},
> - {R_028AB4_VGT_REUSE_OFF, 0, 0},
> - {R_028AB8_VGT_VTX_CNT_EN, 0, 0},
> - {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0},
> {R_028028_DB_STENCIL_CLEAR, 0, 0},
> {R_02802C_DB_DEPTH_CLEAR, 0, 0},
> {GROUP_FORCE_NEW_BLOCK, 0, 0},
> @@ -629,10 +575,7 @@ static const struct r600_reg r600_context_reg_list[] = {
> {R_028404_VGT_MIN_VTX_INDX, 0, 0},
> {R_028408_VGT_INDX_OFFSET, 0, 0},
> {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
> - {R_028A84_VGT_PRIMITIVEID_EN, 0, 0},
> {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
> - {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0},
> - {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0},
> };
>
> /* SHADER RESOURCE R600/R700 */
> @@ -898,8 +841,8 @@ int r600_context_init(struct r600_context *ctx)
> goto out_err;
>
> ctx->cs = ctx->ws->cs_create(ctx->ws);
> + r600_emit_atom(ctx, &ctx->atom_start_cs.atom);
>
> - r600_init_cs(ctx);
> ctx->max_db = 4;
> return 0;
> out_err:
> @@ -1419,7 +1362,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
> bool queries_suspended = false;
> bool streamout_suspended = false;
>
> - if (cs->cdw == ctx->init_dwords)
> + if (cs->cdw == ctx->atom_start_cs.atom.num_dw)
> return;
>
> /* suspend queries */
> @@ -1448,7 +1391,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
> ctx->pm4_dirty_cdwords = 0;
> ctx->flags = 0;
>
> - r600_init_cs(ctx);
> + r600_emit_atom(ctx, &ctx->atom_start_cs.atom);
>
> if (streamout_suspended) {
> ctx->streamout_start = TRUE;
> diff --git a/src/gallium/drivers/r600/r600_hw_context_priv.h b/src/gallium/drivers/r600/r600_hw_context_priv.h
> index 278bc0d..1e57138 100644
> --- a/src/gallium/drivers/r600/r600_hw_context_priv.h
> +++ b/src/gallium/drivers/r600/r600_hw_context_priv.h
> @@ -60,7 +60,6 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
> void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
> int dirty, int index);
> int r600_setup_block_table(struct r600_context *ctx);
> -void r600_init_cs(struct r600_context *ctx);
> int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base);
>
> /*
> diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
> index 5ea8bb8..db976d9 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -207,6 +207,7 @@ static void r600_destroy_context(struct pipe_context *context)
>
> r600_update_num_contexts(rctx->screen, -1);
>
> + r600_release_command_buffer(&rctx->atom_start_cs);
> FREE(rctx);
> }
>
> @@ -247,21 +248,21 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
> case R600:
> case R700:
> r600_init_state_functions(rctx);
> + r600_init_atom_start_cs(rctx);
> if (r600_context_init(rctx)) {
> r600_destroy_context(&rctx->context);
> return NULL;
> }
> - r600_init_config(rctx);
> rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
> break;
> case EVERGREEN:
> case CAYMAN:
> evergreen_init_state_functions(rctx);
> + evergreen_init_atom_start_cs(rctx);
> if (evergreen_context_init(rctx)) {
> r600_destroy_context(&rctx->context);
> return NULL;
> }
> - evergreen_init_config(rctx);
> rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
> break;
> default:
> diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
> index 8eaa988..8889ba7 100644
> --- a/src/gallium/drivers/r600/r600_pipe.h
> +++ b/src/gallium/drivers/r600/r600_pipe.h
> @@ -67,6 +67,14 @@ struct r600_atom {
> struct list_head head;
> };
>
> +/* This is an atom containing GPU commands that never change.
> + * This is supposed to be copied directly into the CS. */
> +struct r600_command_buffer {
> + struct r600_atom atom;
> + uint32_t *buf;
> + unsigned max_num_dw;
> +};
> +
> struct r600_atom_surface_sync {
> struct r600_atom atom;
> unsigned flush_flags; /* CP_COHER_CNTL */
> @@ -245,7 +253,6 @@ struct r600_context {
> struct pipe_stencil_ref stencil_ref;
> struct pipe_viewport_state viewport;
> struct pipe_clip_state clip;
> - struct r600_pipe_state config;
> struct r600_pipe_shader *ps_shader;
> struct r600_pipe_shader *vs_shader;
> struct r600_pipe_state vs_const_buffer;
> @@ -277,6 +284,7 @@ struct r600_context {
>
> /* States based on r600_state. */
> struct list_head dirty_states;
> + struct r600_command_buffer atom_start_cs; /* invariant state mostly */
> struct r600_atom_surface_sync atom_surface_sync;
> struct r600_atom atom_r6xx_flush_and_inv;
>
> @@ -292,7 +300,6 @@ struct r600_context {
> struct list_head enable_list;
> unsigned pm4_dirty_cdwords;
> unsigned ctx_pm4_ndwords;
> - unsigned init_dwords;
>
> /* The list of active queries. Only one query of each type can be active. */
> struct list_head active_query_list;
> @@ -336,7 +343,7 @@ static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *
>
> /* evergreen_state.c */
> void evergreen_init_state_functions(struct r600_context *rctx);
> -void evergreen_init_config(struct r600_context *rctx);
> +void evergreen_init_atom_start_cs(struct r600_context *rctx);
> void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
> void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
> void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
> @@ -394,7 +401,7 @@ int r600_find_vs_semantic_index(struct r600_shader *vs,
> /* r600_state.c */
> void r600_update_sampler_states(struct r600_context *rctx);
> void r600_init_state_functions(struct r600_context *rctx);
> -void r600_init_config(struct r600_context *rctx);
> +void r600_init_atom_start_cs(struct r600_context *rctx);
> void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
> void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
> void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
> @@ -479,6 +486,58 @@ unsigned r600_tex_mipfilter(unsigned filter);
> unsigned r600_tex_compare(unsigned compare);
>
> /*
> + * Helpers for building command buffers
> + */
> +
> +#define PKT3_SET_CONFIG_REG 0x68
> +#define PKT3_SET_CONTEXT_REG 0x69
> +
> +#define R600_CONFIG_REG_OFFSET 0x8000
> +#define R600_CONTEXT_REG_OFFSET 0x28000
> +
> +#define PKT_TYPE_S(x) (((x) & 0x3) << 30)
> +#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
> +#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
> +#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
> +#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
> +
> +static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
> +{
> + cb->buf[cb->atom.num_dw++] = value;
> +}
> +
> +static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
> +{
> + assert(reg < R600_CONTEXT_REG_OFFSET);
> + assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
> + cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
> + cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
> +}
> +
> +static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
> +{
> + assert(reg >= R600_CONTEXT_REG_OFFSET);
> + assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
> + cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
> + cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
> +}
> +
> +static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
> +{
> + r600_store_config_reg_seq(cb, reg, 1);
> + r600_store_value(cb, value);
> +}
> +
> +static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
> +{
> + r600_store_context_reg_seq(cb, reg, 1);
> + r600_store_value(cb, value);
> +}
> +
> +void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
> +void r600_release_command_buffer(struct r600_command_buffer *cb);
> +
> +/*
> * common helpers
> */
> static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
> diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
> index bbba9a2..939bbe4 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -1787,7 +1787,7 @@ void r600_adjust_gprs(struct r600_context *rctx)
> r600_context_pipe_state_set(rctx, &rstate);
> }
>
> -void r600_init_config(struct r600_context *rctx)
> +void r600_init_atom_start_cs(struct r600_context *rctx)
> {
> int ps_prio;
> int vs_prio;
> @@ -1807,9 +1807,21 @@ void r600_init_config(struct r600_context *rctx)
> int num_gs_stack_entries;
> int num_es_stack_entries;
> enum radeon_family family;
> - struct r600_pipe_state *rstate = &rctx->config;
> + struct r600_command_buffer *cb = &rctx->atom_start_cs;
> uint32_t tmp;
>
> + r600_init_command_buffer(cb, 256, EMIT_EARLY);
> +
> + /* R6xx requires this packet at the start of each command buffer */
> + if (rctx->chip_class == R600) {
> + r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
> + r600_store_value(cb, 0);
> + }
> + /* All asics require this one */
> + r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
> + r600_store_value(cb, 0x80000000);
> + r600_store_value(cb, 0x80000000);
> +
> family = rctx->family;
> ps_prio = 0;
> vs_prio = 1;
> @@ -1931,8 +1943,7 @@ void r600_init_config(struct r600_context *rctx)
>
> rctx->default_ps_gprs = num_ps_gprs;
> rctx->default_vs_gprs = num_vs_gprs;
> -
> - rstate->id = R600_PIPE_STATE_CONFIG;
> + rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
>
> /* SQ_CONFIG */
> tmp = 0;
> @@ -1953,91 +1964,82 @@ void r600_init_config(struct r600_context *rctx)
> tmp |= S_008C00_VS_PRIO(vs_prio);
> tmp |= S_008C00_GS_PRIO(gs_prio);
> tmp |= S_008C00_ES_PRIO(es_prio);
> - r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
> -
> - /* SQ_GPR_RESOURCE_MGMT_1 */
> - tmp = 0;
> - tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
> - tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
> - tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
> - rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
> - r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
> + r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
>
> /* SQ_GPR_RESOURCE_MGMT_2 */
> - tmp = 0;
> - tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
> + tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
> tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
> - r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
> + r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
> + r600_store_value(cb, tmp);
>
> /* SQ_THREAD_RESOURCE_MGMT */
> - tmp = 0;
> - tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
> + tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
> tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
> tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
> tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
> - r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
>
> /* SQ_STACK_RESOURCE_MGMT_1 */
> - tmp = 0;
> - tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
> + tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
> tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
> - r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
>
> /* SQ_STACK_RESOURCE_MGMT_2 */
> - tmp = 0;
> - tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
> + tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
> tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
> - r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
> + r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
> +
> + r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
>
> - r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, NULL, 0);
> + r600_store_context_reg(cb, R_028350_SX_MISC, 0);
>
> if (rctx->chip_class >= R700) {
> - r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, NULL, 0);
> + r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
> + r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
> + r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
> + r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
> } else {
> - r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, NULL, 0);
> + r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
> + r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
> + r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
> + r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
> }
> - r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, NULL, 0);
> -
> - r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, NULL, 0);
> - r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, NULL, 0);
> - r600_context_pipe_state_set(rctx, rstate);
> -
> - r600_set_seamless_cubemap(rctx, FALSE);
> + r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
> + r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
> + r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
> +
> + r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
> + r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
> + r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
> + r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
> + r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
> + r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
> + r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
> + r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
> + r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
> + r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
> + r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
> + r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
> + r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
> + r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
> +
> + r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
> + r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
> + r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
> +
> + r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
> + r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
> + r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
> + r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
> +
> + r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
> }
>
> void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
> diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
> index 36b3d53..031f200 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -34,6 +34,30 @@
> #include "r600_pipe.h"
> #include "r600d.h"
>
> +static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
> +{
> + struct radeon_winsys_cs *cs = rctx->cs;
> + struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
> +
> + assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
> + memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
> + cs->cdw += cb->atom.num_dw;
> +}
> +
> +void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
> +{
> + cb->atom.emit = r600_emit_command_buffer;
> + cb->atom.num_dw = 0;
> + cb->atom.flags = flags;
> + cb->buf = CALLOC(1, 4 * num_dw);
> + cb->max_num_dw = num_dw;
> +}
> +
> +void r600_release_command_buffer(struct r600_command_buffer *cb)
> +{
> + FREE(cb->buf);
> +}
> +
> static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
> {
> struct radeon_winsys_cs *cs = rctx->cs;
> diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
> index 3c3238a..40a0db0 100644
> --- a/src/gallium/drivers/r600/r600d.h
> +++ b/src/gallium/drivers/r600/r600d.h
> @@ -36,9 +36,7 @@
> #define EG_BOOL_CONST_OFFSET 0x0003A500
> #define EG_BOOL_CONST_END 0x0003A506
>
> -#define R600_CONFIG_REG_OFFSET 0X00008000
> #define R600_CONFIG_REG_END 0X0000AC00
> -#define R600_CONTEXT_REG_OFFSET 0X00028000
> #define R600_CONTEXT_REG_END 0X00029000
> #define R600_ALU_CONST_OFFSET 0X00030000
> #define R600_ALU_CONST_END 0X00032000
> @@ -158,7 +156,6 @@
> #define PKT3_IT_OPCODE_C 0xFFFF00FF
> #define PKT3_PRED_S(x) (((x) >> 0) & 0x1)
> #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
> -#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PRED_S(predicate))
>
> /* Registers */
> #define R_008490_CP_STRMOUT_CNTL 0x008490
> --
> 1.7.5.4
>
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