[Mesa-dev] [PATCH 1/2] i965: fix wrong urb entries per attr for platform under SNB

[Liu Aleaxander]

For SNB+, One attribute takes 2 urb entries. While for platform under
SNB, we write 4 MRF registers for each attribute, thus it takes 4 urb
entries, right?

NOTE: this is a candidate for stable release branches.
----
  I didn't see this fix anything, meanwhile I didn't see this broke
  anything so far. Since this patch is a need for the next patch, thus
  I put the NOTE here.

Signed-off-by: Yuanhan Liu <yuanhan.liu at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_fs.cpp |    3 +--
 src/mesa/drivers/dri/i965/brw_fs.h   |   20 ++++++++++++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index bf59da3..cbbef11 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -712,8 +712,7 @@ fs_visitor::calculate_urb_setup()
       }
    }

-   /* Each attribute is 4 setup channels, each of which is half a reg. */
-   c->prog_data.urb_read_length = urb_next * 2;
+   c->prog_data.urb_read_length = urb_next * urb_entries_per_attr;
 }

 void
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 0a37b39..1b4f2e3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -406,6 +406,24 @@ public:
       this->kill_emitted = false;
       this->force_uncompressed_stack = 0;
       this->force_sechalf_stack = 0;
+
+      /*
+       * For SNB+, there is a clear saying about this at page 351 of PRM Volume
+       * 2 Part 1:
+       *
+       *   Setup Data (Attribute Vertex Deltas)
+       *
+       *   Output data from the SF stage is delivered in the PS thread payload.
+       *   The amount of data is determined by the Number of Output Attributes
+       *   field in 3DSTATE_SF. Each register contains two channels of one
+       *   attribute. Thus, the total number of registers sent is equal to
+       *   2 * Number of Output Attributes.
+       *
+       * But ther is no such clear saying for platform under SNB. Well, the
+       * data is written by SF thread we wrote, and we write 4 MRF registers
+       * for each attribute.
+       */
+      this->urb_entries_per_attr = intel->gen < 6 ? 4 : 2;
    }

    ~fs_visitor()
@@ -624,6 +642,8 @@ public:

    int force_uncompressed_stack;
    int force_sechalf_stack;
+
+   int urb_entries_per_attr;
 };

 bool brw_do_channel_expressions(struct exec_list *instructions);
-- 
1.7.3.1