[Mesa-dev] [PATCH] i965: Actually enable SIMD16 dispatch on Ivybridge.

[Kenneth Graunke]

Commit acf82657f4d607e4477f03752613d42f239e4bd3 supposedly enabled
SIMD16 dispatch, but neglected to set the "16 Pixel Dispatch Enable"
bit, so nothing actually got enabled.

Furthermore, it neglected to set up the Dispatch GRF Start Register for
kernel 2, which is the SIMD16 program.

Increases performance in Nexuiz by ~15% (n=3).

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/gen7_wm_state.c |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

Embarassing that I forgot this, but hey, I'll take the free FPS... :)

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index d756f7b..5045991 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -163,13 +163,18 @@ upload_ps_state(struct brw_context *brw)
    if (brw->fragment_program->Base.InputsRead != 0)
       dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 
-   if (brw->wm.prog_data->dispatch_width == 8)
+   if (brw->wm.prog_data->dispatch_width == 8) {
       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
-   else
+      if (brw->wm.prog_data->prog_offset_16)
+	 dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
+   } else {
       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
+   }
 
    dw5 |= (brw->wm.prog_data->first_curbe_grf <<
 	   GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
+   dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+	   GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
 
    BEGIN_BATCH(8);
    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
-- 
1.7.7.5