[Mesa-dev] [PATCH 1/6] tgsi: Add output_mode to struct tgsi_opcode_info v2
Tom Stellard
tstellar at gmail.com
Mon Jan 16 11:44:30 PST 2012
v2:
- Rename output_type to output_mode
- Add shorthand definitions for TGSI_OUTPUT_*
---
src/gallium/auxiliary/tgsi/tgsi_info.c | 329 ++++++++++++++++----------------
src/gallium/auxiliary/tgsi/tgsi_info.h | 34 ++++
2 files changed, 201 insertions(+), 162 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 5b26d8f..2407448 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -29,171 +29,176 @@
#include "util/u_memory.h"
#include "tgsi_info.h"
+#define NONE TGSI_OUTPUT_NONE
+#define COMP TGSI_OUTPUT_COMPONENTWISE
+#define REPL TGSI_OUTPUT_REPLICATE
+#define CHAN TGSI_OUTPUT_CHAN_DEPENDENT
+#define OTHR TGSI_OUTPUT_OTHER
+
static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{
- { 1, 1, 0, 0, 0, 0, "ARL", TGSI_OPCODE_ARL },
- { 1, 1, 0, 0, 0, 0, "MOV", TGSI_OPCODE_MOV },
- { 1, 1, 0, 0, 0, 0, "LIT", TGSI_OPCODE_LIT },
- { 1, 1, 0, 0, 0, 0, "RCP", TGSI_OPCODE_RCP },
- { 1, 1, 0, 0, 0, 0, "RSQ", TGSI_OPCODE_RSQ },
- { 1, 1, 0, 0, 0, 0, "EXP", TGSI_OPCODE_EXP },
- { 1, 1, 0, 0, 0, 0, "LOG", TGSI_OPCODE_LOG },
- { 1, 2, 0, 0, 0, 0, "MUL", TGSI_OPCODE_MUL },
- { 1, 2, 0, 0, 0, 0, "ADD", TGSI_OPCODE_ADD },
- { 1, 2, 0, 0, 0, 0, "DP3", TGSI_OPCODE_DP3 },
- { 1, 2, 0, 0, 0, 0, "DP4", TGSI_OPCODE_DP4 },
- { 1, 2, 0, 0, 0, 0, "DST", TGSI_OPCODE_DST },
- { 1, 2, 0, 0, 0, 0, "MIN", TGSI_OPCODE_MIN },
- { 1, 2, 0, 0, 0, 0, "MAX", TGSI_OPCODE_MAX },
- { 1, 2, 0, 0, 0, 0, "SLT", TGSI_OPCODE_SLT },
- { 1, 2, 0, 0, 0, 0, "SGE", TGSI_OPCODE_SGE },
- { 1, 3, 0, 0, 0, 0, "MAD", TGSI_OPCODE_MAD },
- { 1, 2, 0, 0, 0, 0, "SUB", TGSI_OPCODE_SUB },
- { 1, 3, 0, 0, 0, 0, "LRP", TGSI_OPCODE_LRP },
- { 1, 3, 0, 0, 0, 0, "CND", TGSI_OPCODE_CND },
- { 0, 0, 0, 0, 0, 0, "", 20 }, /* removed */
- { 1, 3, 0, 0, 0, 0, "DP2A", TGSI_OPCODE_DP2A },
- { 0, 0, 0, 0, 0, 0, "", 22 }, /* removed */
- { 0, 0, 0, 0, 0, 0, "", 23 }, /* removed */
- { 1, 1, 0, 0, 0, 0, "FRC", TGSI_OPCODE_FRC },
- { 1, 3, 0, 0, 0, 0, "CLAMP", TGSI_OPCODE_CLAMP },
- { 1, 1, 0, 0, 0, 0, "FLR", TGSI_OPCODE_FLR },
- { 1, 1, 0, 0, 0, 0, "ROUND", TGSI_OPCODE_ROUND },
- { 1, 1, 0, 0, 0, 0, "EX2", TGSI_OPCODE_EX2 },
- { 1, 1, 0, 0, 0, 0, "LG2", TGSI_OPCODE_LG2 },
- { 1, 2, 0, 0, 0, 0, "POW", TGSI_OPCODE_POW },
- { 1, 2, 0, 0, 0, 0, "XPD", TGSI_OPCODE_XPD },
- { 0, 0, 0, 0, 0, 0, "", 32 }, /* removed */
- { 1, 1, 0, 0, 0, 0, "ABS", TGSI_OPCODE_ABS },
- { 1, 1, 0, 0, 0, 0, "RCC", TGSI_OPCODE_RCC },
- { 1, 2, 0, 0, 0, 0, "DPH", TGSI_OPCODE_DPH },
- { 1, 1, 0, 0, 0, 0, "COS", TGSI_OPCODE_COS },
- { 1, 1, 0, 0, 0, 0, "DDX", TGSI_OPCODE_DDX },
- { 1, 1, 0, 0, 0, 0, "DDY", TGSI_OPCODE_DDY },
- { 0, 0, 0, 0, 0, 0, "KILP", TGSI_OPCODE_KILP },
- { 1, 1, 0, 0, 0, 0, "PK2H", TGSI_OPCODE_PK2H },
- { 1, 1, 0, 0, 0, 0, "PK2US", TGSI_OPCODE_PK2US },
- { 1, 1, 0, 0, 0, 0, "PK4B", TGSI_OPCODE_PK4B },
- { 1, 1, 0, 0, 0, 0, "PK4UB", TGSI_OPCODE_PK4UB },
- { 1, 2, 0, 0, 0, 0, "RFL", TGSI_OPCODE_RFL },
- { 1, 2, 0, 0, 0, 0, "SEQ", TGSI_OPCODE_SEQ },
- { 1, 2, 0, 0, 0, 0, "SFL", TGSI_OPCODE_SFL },
- { 1, 2, 0, 0, 0, 0, "SGT", TGSI_OPCODE_SGT },
- { 1, 1, 0, 0, 0, 0, "SIN", TGSI_OPCODE_SIN },
- { 1, 2, 0, 0, 0, 0, "SLE", TGSI_OPCODE_SLE },
- { 1, 2, 0, 0, 0, 0, "SNE", TGSI_OPCODE_SNE },
- { 1, 2, 0, 0, 0, 0, "STR", TGSI_OPCODE_STR },
- { 1, 2, 1, 0, 0, 0, "TEX", TGSI_OPCODE_TEX },
- { 1, 4, 1, 0, 0, 0, "TXD", TGSI_OPCODE_TXD },
- { 1, 2, 1, 0, 0, 0, "TXP", TGSI_OPCODE_TXP },
- { 1, 1, 0, 0, 0, 0, "UP2H", TGSI_OPCODE_UP2H },
- { 1, 1, 0, 0, 0, 0, "UP2US", TGSI_OPCODE_UP2US },
- { 1, 1, 0, 0, 0, 0, "UP4B", TGSI_OPCODE_UP4B },
- { 1, 1, 0, 0, 0, 0, "UP4UB", TGSI_OPCODE_UP4UB },
- { 1, 3, 0, 0, 0, 0, "X2D", TGSI_OPCODE_X2D },
- { 1, 1, 0, 0, 0, 0, "ARA", TGSI_OPCODE_ARA },
- { 1, 1, 0, 0, 0, 0, "ARR", TGSI_OPCODE_ARR },
- { 0, 1, 0, 0, 0, 0, "BRA", TGSI_OPCODE_BRA },
- { 0, 0, 0, 1, 0, 0, "CAL", TGSI_OPCODE_CAL },
- { 0, 0, 0, 0, 0, 0, "RET", TGSI_OPCODE_RET },
- { 1, 1, 0, 0, 0, 0, "SSG", TGSI_OPCODE_SSG },
- { 1, 3, 0, 0, 0, 0, "CMP", TGSI_OPCODE_CMP },
- { 1, 1, 0, 0, 0, 0, "SCS", TGSI_OPCODE_SCS },
- { 1, 2, 1, 0, 0, 0, "TXB", TGSI_OPCODE_TXB },
- { 1, 1, 0, 0, 0, 0, "NRM", TGSI_OPCODE_NRM },
- { 1, 2, 0, 0, 0, 0, "DIV", TGSI_OPCODE_DIV },
- { 1, 2, 0, 0, 0, 0, "DP2", TGSI_OPCODE_DP2 },
- { 1, 2, 1, 0, 0, 0, "TXL", TGSI_OPCODE_TXL },
- { 0, 0, 0, 0, 0, 0, "BRK", TGSI_OPCODE_BRK },
- { 0, 1, 0, 1, 0, 1, "IF", TGSI_OPCODE_IF },
- { 1, 1, 0, 0, 0, 1, "", 75 }, /* removed */
- { 0, 1, 0, 0, 0, 1, "", 76 }, /* removed */
- { 0, 0, 0, 1, 1, 1, "ELSE", TGSI_OPCODE_ELSE },
- { 0, 0, 0, 0, 1, 0, "ENDIF", TGSI_OPCODE_ENDIF },
- { 1, 0, 0, 0, 1, 0, "", 79 }, /* removed */
- { 0, 0, 0, 0, 1, 0, "", 80 }, /* removed */
- { 0, 1, 0, 0, 0, 0, "PUSHA", TGSI_OPCODE_PUSHA },
- { 1, 0, 0, 0, 0, 0, "POPA", TGSI_OPCODE_POPA },
- { 1, 1, 0, 0, 0, 0, "CEIL", TGSI_OPCODE_CEIL },
- { 1, 1, 0, 0, 0, 0, "I2F", TGSI_OPCODE_I2F },
- { 1, 1, 0, 0, 0, 0, "NOT", TGSI_OPCODE_NOT },
- { 1, 1, 0, 0, 0, 0, "TRUNC", TGSI_OPCODE_TRUNC },
- { 1, 2, 0, 0, 0, 0, "SHL", TGSI_OPCODE_SHL },
- { 0, 0, 0, 0, 0, 0, "", 88 }, /* removed */
- { 1, 2, 0, 0, 0, 0, "AND", TGSI_OPCODE_AND },
- { 1, 2, 0, 0, 0, 0, "OR", TGSI_OPCODE_OR },
- { 1, 2, 0, 0, 0, 0, "MOD", TGSI_OPCODE_MOD },
- { 1, 2, 0, 0, 0, 0, "XOR", TGSI_OPCODE_XOR },
- { 1, 3, 0, 0, 0, 0, "SAD", TGSI_OPCODE_SAD },
- { 1, 2, 1, 0, 0, 0, "TXF", TGSI_OPCODE_TXF },
- { 1, 2, 1, 0, 0, 0, "TXQ", TGSI_OPCODE_TXQ },
- { 0, 0, 0, 0, 0, 0, "CONT", TGSI_OPCODE_CONT },
- { 0, 0, 0, 0, 0, 0, "EMIT", TGSI_OPCODE_EMIT },
- { 0, 0, 0, 0, 0, 0, "ENDPRIM", TGSI_OPCODE_ENDPRIM },
- { 0, 0, 0, 1, 0, 1, "BGNLOOP", TGSI_OPCODE_BGNLOOP },
- { 0, 0, 0, 0, 0, 1, "BGNSUB", TGSI_OPCODE_BGNSUB },
- { 0, 0, 0, 1, 1, 0, "ENDLOOP", TGSI_OPCODE_ENDLOOP },
- { 0, 0, 0, 0, 1, 0, "ENDSUB", TGSI_OPCODE_ENDSUB },
- { 0, 0, 0, 0, 0, 0, "", 103 }, /* removed */
- { 0, 0, 0, 0, 0, 0, "", 104 }, /* removed */
- { 0, 0, 0, 0, 0, 0, "", 105 }, /* removed */
- { 0, 0, 0, 0, 0, 0, "", 106 }, /* removed */
- { 0, 0, 0, 0, 0, 0, "NOP", TGSI_OPCODE_NOP },
- { 0, 0, 0, 0, 0, 0, "", 108 }, /* removed */
- { 0, 0, 0, 0, 0, 0, "", 109 }, /* removed */
- { 0, 0, 0, 0, 0, 0, "", 110 }, /* removed */
- { 0, 0, 0, 0, 0, 0, "", 111 }, /* removed */
- { 1, 1, 0, 0, 0, 0, "NRM4", TGSI_OPCODE_NRM4 },
- { 0, 1, 0, 0, 0, 0, "CALLNZ", TGSI_OPCODE_CALLNZ },
- { 0, 1, 0, 0, 0, 0, "IFC", TGSI_OPCODE_IFC },
- { 0, 1, 0, 0, 0, 0, "BREAKC", TGSI_OPCODE_BREAKC },
- { 0, 1, 0, 0, 0, 0, "KIL", TGSI_OPCODE_KIL },
- { 0, 0, 0, 0, 0, 0, "END", TGSI_OPCODE_END },
- { 0, 0, 0, 0, 0, 0, "", 118 }, /* removed */
- { 1, 1, 0, 0, 0, 0, "F2I", TGSI_OPCODE_F2I },
- { 1, 2, 0, 0, 0, 0, "IDIV", TGSI_OPCODE_IDIV },
- { 1, 2, 0, 0, 0, 0, "IMAX", TGSI_OPCODE_IMAX },
- { 1, 2, 0, 0, 0, 0, "IMIN", TGSI_OPCODE_IMIN },
- { 1, 1, 0, 0, 0, 0, "INEG", TGSI_OPCODE_INEG },
- { 1, 2, 0, 0, 0, 0, "ISGE", TGSI_OPCODE_ISGE },
- { 1, 2, 0, 0, 0, 0, "ISHR", TGSI_OPCODE_ISHR },
- { 1, 2, 0, 0, 0, 0, "ISLT", TGSI_OPCODE_ISLT },
- { 1, 1, 0, 0, 0, 0, "F2U", TGSI_OPCODE_F2U },
- { 1, 1, 0, 0, 0, 0, "U2F", TGSI_OPCODE_U2F },
- { 1, 2, 0, 0, 0, 0, "UADD", TGSI_OPCODE_UADD },
- { 1, 2, 0, 0, 0, 0, "UDIV", TGSI_OPCODE_UDIV },
- { 1, 3, 0, 0, 0, 0, "UMAD", TGSI_OPCODE_UMAD },
- { 1, 2, 0, 0, 0, 0, "UMAX", TGSI_OPCODE_UMAX },
- { 1, 2, 0, 0, 0, 0, "UMIN", TGSI_OPCODE_UMIN },
- { 1, 2, 0, 0, 0, 0, "UMOD", TGSI_OPCODE_UMOD },
- { 1, 2, 0, 0, 0, 0, "UMUL", TGSI_OPCODE_UMUL },
- { 1, 2, 0, 0, 0, 0, "USEQ", TGSI_OPCODE_USEQ },
- { 1, 2, 0, 0, 0, 0, "USGE", TGSI_OPCODE_USGE },
- { 1, 2, 0, 0, 0, 0, "USHR", TGSI_OPCODE_USHR },
- { 1, 2, 0, 0, 0, 0, "USLT", TGSI_OPCODE_USLT },
- { 1, 2, 0, 0, 0, 0, "USNE", TGSI_OPCODE_USNE },
- { 0, 1, 0, 0, 0, 0, "SWITCH", TGSI_OPCODE_SWITCH },
- { 0, 1, 0, 0, 0, 0, "CASE", TGSI_OPCODE_CASE },
- { 0, 0, 0, 0, 0, 0, "DEFAULT", TGSI_OPCODE_DEFAULT },
- { 0, 0, 0, 0, 0, 0, "ENDSWITCH", TGSI_OPCODE_ENDSWITCH },
+ { 1, 1, 0, 0, 0, 0, COMP, "ARL", TGSI_OPCODE_ARL },
+ { 1, 1, 0, 0, 0, 0, COMP, "MOV", TGSI_OPCODE_MOV },
+ { 1, 1, 0, 0, 0, 0, CHAN, "LIT", TGSI_OPCODE_LIT },
+ { 1, 1, 0, 0, 0, 0, REPL, "RCP", TGSI_OPCODE_RCP },
+ { 1, 1, 0, 0, 0, 0, REPL, "RSQ", TGSI_OPCODE_RSQ },
+ { 1, 1, 0, 0, 0, 0, CHAN, "EXP", TGSI_OPCODE_EXP },
+ { 1, 1, 0, 0, 0, 0, CHAN, "LOG", TGSI_OPCODE_LOG },
+ { 1, 2, 0, 0, 0, 0, COMP, "MUL", TGSI_OPCODE_MUL },
+ { 1, 2, 0, 0, 0, 0, COMP, "ADD", TGSI_OPCODE_ADD },
+ { 1, 2, 0, 0, 0, 0, REPL, "DP3", TGSI_OPCODE_DP3 },
+ { 1, 2, 0, 0, 0, 0, REPL, "DP4", TGSI_OPCODE_DP4 },
+ { 1, 2, 0, 0, 0, 0, CHAN, "DST", TGSI_OPCODE_DST },
+ { 1, 2, 0, 0, 0, 0, COMP, "MIN", TGSI_OPCODE_MIN },
+ { 1, 2, 0, 0, 0, 0, COMP, "MAX", TGSI_OPCODE_MAX },
+ { 1, 2, 0, 0, 0, 0, COMP, "SLT", TGSI_OPCODE_SLT },
+ { 1, 2, 0, 0, 0, 0, COMP, "SGE", TGSI_OPCODE_SGE },
+ { 1, 3, 0, 0, 0, 0, COMP, "MAD", TGSI_OPCODE_MAD },
+ { 1, 2, 0, 0, 0, 0, COMP, "SUB", TGSI_OPCODE_SUB },
+ { 1, 3, 0, 0, 0, 0, COMP, "LRP", TGSI_OPCODE_LRP },
+ { 1, 3, 0, 0, 0, 0, COMP, "CND", TGSI_OPCODE_CND },
+ { 0, 0, 0, 0, 0, 0, NONE, "", 20 }, /* removed */
+ { 1, 3, 0, 0, 0, 0, REPL, "DP2A", TGSI_OPCODE_DP2A },
+ { 0, 0, 0, 0, 0, 0, NONE, "", 22 }, /* removed */
+ { 0, 0, 0, 0, 0, 0, NONE, "", 23 }, /* removed */
+ { 1, 1, 0, 0, 0, 0, COMP, "FRC", TGSI_OPCODE_FRC },
+ { 1, 3, 0, 0, 0, 0, COMP, "CLAMP", TGSI_OPCODE_CLAMP },
+ { 1, 1, 0, 0, 0, 0, COMP, "FLR", TGSI_OPCODE_FLR },
+ { 1, 1, 0, 0, 0, 0, COMP, "ROUND", TGSI_OPCODE_ROUND },
+ { 1, 1, 0, 0, 0, 0, REPL, "EX2", TGSI_OPCODE_EX2 },
+ { 1, 1, 0, 0, 0, 0, REPL, "LG2", TGSI_OPCODE_LG2 },
+ { 1, 2, 0, 0, 0, 0, REPL, "POW", TGSI_OPCODE_POW },
+ { 1, 2, 0, 0, 0, 0, COMP, "XPD", TGSI_OPCODE_XPD },
+ { 0, 0, 0, 0, 0, 0, NONE, "", 32 }, /* removed */
+ { 1, 1, 0, 0, 0, 0, COMP, "ABS", TGSI_OPCODE_ABS },
+ { 1, 1, 0, 0, 0, 0, REPL, "RCC", TGSI_OPCODE_RCC },
+ { 1, 2, 0, 0, 0, 0, REPL, "DPH", TGSI_OPCODE_DPH },
+ { 1, 1, 0, 0, 0, 0, REPL, "COS", TGSI_OPCODE_COS },
+ { 1, 1, 0, 0, 0, 0, COMP, "DDX", TGSI_OPCODE_DDX },
+ { 1, 1, 0, 0, 0, 0, COMP, "DDY", TGSI_OPCODE_DDY },
+ { 0, 0, 0, 0, 0, 0, NONE, "KILP", TGSI_OPCODE_KILP },
+ { 1, 1, 0, 0, 0, 0, COMP, "PK2H", TGSI_OPCODE_PK2H },
+ { 1, 1, 0, 0, 0, 0, COMP, "PK2US", TGSI_OPCODE_PK2US },
+ { 1, 1, 0, 0, 0, 0, COMP, "PK4B", TGSI_OPCODE_PK4B },
+ { 1, 1, 0, 0, 0, 0, COMP, "PK4UB", TGSI_OPCODE_PK4UB },
+ { 1, 2, 0, 0, 0, 0, COMP, "RFL", TGSI_OPCODE_RFL },
+ { 1, 2, 0, 0, 0, 0, COMP, "SEQ", TGSI_OPCODE_SEQ },
+ { 1, 2, 0, 0, 0, 0, REPL, "SFL", TGSI_OPCODE_SFL },
+ { 1, 2, 0, 0, 0, 0, COMP, "SGT", TGSI_OPCODE_SGT },
+ { 1, 1, 0, 0, 0, 0, REPL, "SIN", TGSI_OPCODE_SIN },
+ { 1, 2, 0, 0, 0, 0, COMP, "SLE", TGSI_OPCODE_SLE },
+ { 1, 2, 0, 0, 0, 0, COMP, "SNE", TGSI_OPCODE_SNE },
+ { 1, 2, 0, 0, 0, 0, REPL, "STR", TGSI_OPCODE_STR },
+ { 1, 2, 1, 0, 0, 0, OTHR, "TEX", TGSI_OPCODE_TEX },
+ { 1, 4, 1, 0, 0, 0, OTHR, "TXD", TGSI_OPCODE_TXD },
+ { 1, 2, 1, 0, 0, 0, OTHR, "TXP", TGSI_OPCODE_TXP },
+ { 1, 1, 0, 0, 0, 0, COMP, "UP2H", TGSI_OPCODE_UP2H },
+ { 1, 1, 0, 0, 0, 0, COMP, "UP2US", TGSI_OPCODE_UP2US },
+ { 1, 1, 0, 0, 0, 0, COMP, "UP4B", TGSI_OPCODE_UP4B },
+ { 1, 1, 0, 0, 0, 0, COMP, "UP4UB", TGSI_OPCODE_UP4UB },
+ { 1, 3, 0, 0, 0, 0, COMP, "X2D", TGSI_OPCODE_X2D },
+ { 1, 1, 0, 0, 0, 0, COMP, "ARA", TGSI_OPCODE_ARA },
+ { 1, 1, 0, 0, 0, 0, COMP, "ARR", TGSI_OPCODE_ARR },
+ { 0, 1, 0, 0, 0, 0, NONE, "BRA", TGSI_OPCODE_BRA },
+ { 0, 0, 0, 1, 0, 0, NONE, "CAL", TGSI_OPCODE_CAL },
+ { 0, 0, 0, 0, 0, 0, NONE, "RET", TGSI_OPCODE_RET },
+ { 1, 1, 0, 0, 0, 0, COMP, "SSG", TGSI_OPCODE_SSG },
+ { 1, 3, 0, 0, 0, 0, COMP, "CMP", TGSI_OPCODE_CMP },
+ { 1, 1, 0, 0, 0, 0, CHAN, "SCS", TGSI_OPCODE_SCS },
+ { 1, 2, 1, 0, 0, 0, OTHR, "TXB", TGSI_OPCODE_TXB },
+ { 1, 1, 0, 0, 0, 0, COMP, "NRM", TGSI_OPCODE_NRM },
+ { 1, 2, 0, 0, 0, 0, COMP, "DIV", TGSI_OPCODE_DIV },
+ { 1, 2, 0, 0, 0, 0, REPL, "DP2", TGSI_OPCODE_DP2 },
+ { 1, 2, 1, 0, 0, 0, OTHR, "TXL", TGSI_OPCODE_TXL },
+ { 0, 0, 0, 0, 0, 0, NONE, "BRK", TGSI_OPCODE_BRK },
+ { 0, 1, 0, 1, 0, 1, NONE, "IF", TGSI_OPCODE_IF },
+ { 1, 1, 0, 0, 0, 1, NONE, "", 75 }, /* removed */
+ { 0, 1, 0, 0, 0, 1, NONE, "", 76 }, /* removed */
+ { 0, 0, 0, 1, 1, 1, NONE, "ELSE", TGSI_OPCODE_ELSE },
+ { 0, 0, 0, 0, 1, 0, NONE, "ENDIF", TGSI_OPCODE_ENDIF },
+ { 1, 0, 0, 0, 1, 0, NONE, "", 79 }, /* removed */
+ { 0, 0, 0, 0, 1, 0, NONE, "", 80 }, /* removed */
+ { 0, 1, 0, 0, 0, 0, NONE, "PUSHA", TGSI_OPCODE_PUSHA },
+ { 1, 0, 0, 0, 0, 0, NONE, "POPA", TGSI_OPCODE_POPA },
+ { 1, 1, 0, 0, 0, 0, COMP, "CEIL", TGSI_OPCODE_CEIL },
+ { 1, 1, 0, 0, 0, 0, COMP, "I2F", TGSI_OPCODE_I2F },
+ { 1, 1, 0, 0, 0, 0, COMP, "NOT", TGSI_OPCODE_NOT },
+ { 1, 1, 0, 0, 0, 0, COMP, "TRUNC", TGSI_OPCODE_TRUNC },
+ { 1, 2, 0, 0, 0, 0, COMP, "SHL", TGSI_OPCODE_SHL },
+ { 0, 0, 0, 0, 0, 0, NONE, "", 88 }, /* removed */
+ { 1, 2, 0, 0, 0, 0, COMP, "AND", TGSI_OPCODE_AND },
+ { 1, 2, 0, 0, 0, 0, COMP, "OR", TGSI_OPCODE_OR },
+ { 1, 2, 0, 0, 0, 0, COMP, "MOD", TGSI_OPCODE_MOD },
+ { 1, 2, 0, 0, 0, 0, COMP, "XOR", TGSI_OPCODE_XOR },
+ { 1, 3, 0, 0, 0, 0, COMP, "SAD", TGSI_OPCODE_SAD },
+ { 1, 2, 1, 0, 0, 0, OTHR, "TXF", TGSI_OPCODE_TXF },
+ { 1, 2, 1, 0, 0, 0, OTHR, "TXQ", TGSI_OPCODE_TXQ },
+ { 0, 0, 0, 0, 0, 0, NONE, "CONT", TGSI_OPCODE_CONT },
+ { 0, 0, 0, 0, 0, 0, NONE, "EMIT", TGSI_OPCODE_EMIT },
+ { 0, 0, 0, 0, 0, 0, NONE, "ENDPRIM", TGSI_OPCODE_ENDPRIM },
+ { 0, 0, 0, 1, 0, 1, NONE, "BGNLOOP", TGSI_OPCODE_BGNLOOP },
+ { 0, 0, 0, 0, 0, 1, NONE, "BGNSUB", TGSI_OPCODE_BGNSUB },
+ { 0, 0, 0, 1, 1, 0, NONE, "ENDLOOP", TGSI_OPCODE_ENDLOOP },
+ { 0, 0, 0, 0, 1, 0, NONE, "ENDSUB", TGSI_OPCODE_ENDSUB },
+ { 0, 0, 0, 0, 0, 0, NONE, "", 103 }, /* removed */
+ { 0, 0, 0, 0, 0, 0, NONE, "", 104 }, /* removed */
+ { 0, 0, 0, 0, 0, 0, NONE, "", 105 }, /* removed */
+ { 0, 0, 0, 0, 0, 0, NONE, "", 106 }, /* removed */
+ { 0, 0, 0, 0, 0, 0, NONE, "NOP", TGSI_OPCODE_NOP },
+ { 0, 0, 0, 0, 0, 0, NONE, "", 108 }, /* removed */
+ { 0, 0, 0, 0, 0, 0, NONE, "", 109 }, /* removed */
+ { 0, 0, 0, 0, 0, 0, NONE, "", 110 }, /* removed */
+ { 0, 0, 0, 0, 0, 0, NONE, "", 111 }, /* removed */
+ { 1, 1, 0, 0, 0, 0, REPL, "NRM4", TGSI_OPCODE_NRM4 },
+ { 0, 1, 0, 0, 0, 0, NONE, "CALLNZ", TGSI_OPCODE_CALLNZ },
+ { 0, 1, 0, 0, 0, 0, NONE, "IFC", TGSI_OPCODE_IFC },
+ { 0, 1, 0, 0, 0, 0, NONE, "BREAKC", TGSI_OPCODE_BREAKC },
+ { 0, 1, 0, 0, 0, 0, NONE, "KIL", TGSI_OPCODE_KIL },
+ { 0, 0, 0, 0, 0, 0, NONE, "END", TGSI_OPCODE_END },
+ { 0, 0, 0, 0, 0, 0, NONE, "", 118 }, /* removed */
+ { 1, 1, 0, 0, 0, 0, COMP, "F2I", TGSI_OPCODE_F2I },
+ { 1, 2, 0, 0, 0, 0, COMP, "IDIV", TGSI_OPCODE_IDIV },
+ { 1, 2, 0, 0, 0, 0, COMP, "IMAX", TGSI_OPCODE_IMAX },
+ { 1, 2, 0, 0, 0, 0, COMP, "IMIN", TGSI_OPCODE_IMIN },
+ { 1, 1, 0, 0, 0, 0, COMP, "INEG", TGSI_OPCODE_INEG },
+ { 1, 2, 0, 0, 0, 0, COMP, "ISGE", TGSI_OPCODE_ISGE },
+ { 1, 2, 0, 0, 0, 0, COMP, "ISHR", TGSI_OPCODE_ISHR },
+ { 1, 2, 0, 0, 0, 0, COMP, "ISLT", TGSI_OPCODE_ISLT },
+ { 1, 1, 0, 0, 0, 0, COMP, "F2U", TGSI_OPCODE_F2U },
+ { 1, 1, 0, 0, 0, 0, COMP, "U2F", TGSI_OPCODE_U2F },
+ { 1, 2, 0, 0, 0, 0, COMP, "UADD", TGSI_OPCODE_UADD },
+ { 1, 2, 0, 0, 0, 0, COMP, "UDIV", TGSI_OPCODE_UDIV },
+ { 1, 3, 0, 0, 0, 0, COMP, "UMAD", TGSI_OPCODE_UMAD },
+ { 1, 2, 0, 0, 0, 0, COMP, "UMAX", TGSI_OPCODE_UMAX },
+ { 1, 2, 0, 0, 0, 0, COMP, "UMIN", TGSI_OPCODE_UMIN },
+ { 1, 2, 0, 0, 0, 0, COMP, "UMOD", TGSI_OPCODE_UMOD },
+ { 1, 2, 0, 0, 0, 0, COMP, "UMUL", TGSI_OPCODE_UMUL },
+ { 1, 2, 0, 0, 0, 0, COMP, "USEQ", TGSI_OPCODE_USEQ },
+ { 1, 2, 0, 0, 0, 0, COMP, "USGE", TGSI_OPCODE_USGE },
+ { 1, 2, 0, 0, 0, 0, COMP, "USHR", TGSI_OPCODE_USHR },
+ { 1, 2, 0, 0, 0, 0, COMP, "USLT", TGSI_OPCODE_USLT },
+ { 1, 2, 0, 0, 0, 0, COMP, "USNE", TGSI_OPCODE_USNE },
+ { 0, 1, 0, 0, 0, 0, NONE, "SWITCH", TGSI_OPCODE_SWITCH },
+ { 0, 1, 0, 0, 0, 0, NONE, "CASE", TGSI_OPCODE_CASE },
+ { 0, 0, 0, 0, 0, 0, NONE, "DEFAULT", TGSI_OPCODE_DEFAULT },
+ { 0, 0, 0, 0, 0, 0, NONE, "ENDSWITCH", TGSI_OPCODE_ENDSWITCH },
- { 1, 2, 0, 0, 0, 0, "LOAD", TGSI_OPCODE_LOAD },
- { 1, 2, 0, 0, 0, 0, "LOAD_MS", TGSI_OPCODE_LOAD_MS },
- { 1, 3, 0, 0, 0, 0, "SAMPLE", TGSI_OPCODE_SAMPLE },
- { 1, 4, 0, 0, 0, 0, "SAMPLE_B", TGSI_OPCODE_SAMPLE_B },
- { 1, 4, 0, 0, 0, 0, "SAMPLE_C", TGSI_OPCODE_SAMPLE_C },
- { 1, 4, 0, 0, 0, 0, "SAMPLE_C_LZ", TGSI_OPCODE_SAMPLE_C_LZ },
- { 1, 5, 0, 0, 0, 0, "SAMPLE_D", TGSI_OPCODE_SAMPLE_D },
- { 1, 3, 0, 0, 0, 0, "SAMPLE_L", TGSI_OPCODE_SAMPLE_L },
- { 1, 3, 0, 0, 0, 0, "GATHER4", TGSI_OPCODE_GATHER4 },
- { 1, 2, 0, 0, 0, 0, "RESINFO", TGSI_OPCODE_RESINFO },
- { 1, 2, 0, 0, 0, 0, "SAMPLE_POS", TGSI_OPCODE_SAMPLE_POS },
- { 1, 2, 0, 0, 0, 0, "SAMPLE_INFO", TGSI_OPCODE_SAMPLE_INFO },
-
- { 1, 1, 0, 0, 0, 0, "UARL", TGSI_OPCODE_UARL },
- { 1, 3, 0, 0, 0, 0, "UCMP", TGSI_OPCODE_UCMP },
- { 1, 1, 0, 0, 0, 0, "IABS", TGSI_OPCODE_IABS },
- { 1, 1, 0, 0, 0, 0, "ISSG", TGSI_OPCODE_ISSG },
+ { 1, 2, 0, 0, 0, 0, OTHR, "LOAD", TGSI_OPCODE_LOAD },
+ { 1, 2, 0, 0, 0, 0, OTHR, "LOAD_MS", TGSI_OPCODE_LOAD_MS },
+ { 1, 3, 0, 0, 0, 0, OTHR, "SAMPLE", TGSI_OPCODE_SAMPLE },
+ { 1, 4, 0, 0, 0, 0, OTHR, "SAMPLE_B", TGSI_OPCODE_SAMPLE_B },
+ { 1, 4, 0, 0, 0, 0, OTHR, "SAMPLE_C", TGSI_OPCODE_SAMPLE_C },
+ { 1, 4, 0, 0, 0, 0, OTHR, "SAMPLE_C_LZ", TGSI_OPCODE_SAMPLE_C_LZ },
+ { 1, 5, 0, 0, 0, 0, OTHR, "SAMPLE_D", TGSI_OPCODE_SAMPLE_D },
+ { 1, 3, 0, 0, 0, 0, OTHR, "SAMPLE_L", TGSI_OPCODE_SAMPLE_L },
+ { 1, 3, 0, 0, 0, 0, OTHR, "GATHER4", TGSI_OPCODE_GATHER4 },
+ { 1, 2, 0, 0, 0, 0, OTHR, "RESINFO", TGSI_OPCODE_RESINFO },
+ { 1, 2, 0, 0, 0, 0, OTHR, "SAMPLE_POS", TGSI_OPCODE_SAMPLE_POS },
+ { 1, 2, 0, 0, 0, 0, OTHR, "SAMPLE_INFO", TGSI_OPCODE_SAMPLE_INFO },
+ { 1, 1, 0, 0, 0, 0, COMP, "UARL", TGSI_OPCODE_UARL },
+ { 1, 3, 0, 0, 0, 0, COMP, "UCMP", TGSI_OPCODE_UCMP },
+ { 1, 1, 0, 0, 0, 0, COMP, "IABS", TGSI_OPCODE_IABS },
+ { 1, 1, 0, 0, 0, 0, COMP, "ISSG", TGSI_OPCODE_ISSG },
};
const struct tgsi_opcode_info *
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.h b/src/gallium/auxiliary/tgsi/tgsi_info.h
index 1992d11..c0427fb 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.h
@@ -35,6 +35,39 @@
extern "C" {
#endif
+/* This enum describes how an opcode calculates its result. */
+enum tgsi_output_mode {
+ /** The opcode produces no result. */
+ TGSI_OUTPUT_NONE = 0,
+
+ /** When this opcode writes to a channel of the destination register,
+ * it takes as arguments values from the same channel of the source
+ * register(s).
+ *
+ * Example: TGSI_OPCODE_ADD
+ */
+ TGSI_OUTPUT_COMPONENTWISE = 1,
+
+ /** This opcode writes the same value to all enabled channels of the
+ * destination register.
+ *
+ * Example: TGSI_OPCODE_RSQ
+ */
+ TGSI_OUTPUT_REPLICATE = 2,
+
+ /** The operation performed by this opcode is dependent on which channel
+ * of the destination register is being written.
+ *
+ * Example: TGSI_OPCODE_LOG
+ */
+ TGSI_OUTPUT_CHAN_DEPENDENT = 3,
+
+ /**
+ * Example: TGSI_OPCODE_TEX
+ */
+ TGSI_OUTPUT_OTHER = 4
+};
+
struct tgsi_opcode_info
{
unsigned num_dst:3;
@@ -43,6 +76,7 @@ struct tgsi_opcode_info
unsigned is_branch:1;
int pre_dedent:2;
int post_indent:2;
+ enum tgsi_output_mode output_mode:3;
const char *mnemonic;
uint opcode;
};
--
1.7.6
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