[Mesa-dev] [PATCH 6/7] i965/blorp: Loosen assertions in compute_msaa_layout_for_pipeline.

[Anuj Phogat]

On Thu, Jul 12, 2012 at 10:43 AM, Paul Berry <stereotype441 at gmail.com> wrote:
> Previously, on Gen7, compute_msaa_layout_for_pipeline() would verify
> that IMS layout is not used.  However, now that we configure
> SURFACE_STATE correctly for IMS surfaces, IMS layout is available.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |    9 ++-------
>  1 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index c8db662..c5e0ef9 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -1432,20 +1432,15 @@ compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples,
>        assert(true_layout == INTEL_MSAA_LAYOUT_NONE ||
>               true_layout == INTEL_MSAA_LAYOUT_IMS);
>        return INTEL_MSAA_LAYOUT_NONE;
> +   } else {
> +      assert(true_layout != INTEL_MSAA_LAYOUT_NONE);
>     }
>
>     /* Prior to Gen7, all MSAA surfaces use IMS layout. */
>     if (brw->intel.gen == 6) {
>        assert(true_layout == INTEL_MSAA_LAYOUT_IMS);
> -      return INTEL_MSAA_LAYOUT_IMS;
>     }
>
> -   /* Since blorp uses color textures and render targets to do all its work
> -    * (even when blitting stencil and depth data), we always have to configure
> -    * the Gen7 GPU to use UMS or CMS layout on Gen7.
> -    */
> -   assert(true_layout == INTEL_MSAA_LAYOUT_UMS ||
> -          true_layout == INTEL_MSAA_LAYOUT_CMS);
>     return true_layout;
>  }
>
> --
> 1.7.7.6
>

Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>