[Mesa-dev] [PATCH 1/2] i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.

[Chad Versace]

On 04/26/2012 06:54 AM, Paul Berry wrote:
> In i965 Gen6, Mesa has for a long time used the "depth coordinate
> offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
> render to miplevels other than 0.  Unfortunately, this doesn't work,
> because these offsets must be aligned to multiples of 8, and miplevels
> in the depth buffer are only guaranteed to be aligned to multiples of
> 4.  When the offsets aren't aligned to a multiple of 8, the GPU
> sometimes hangs.
> 
> As a temporary measure, to avoid GPU hangs, this patch smashes the 3
> LSB's of "depth coordinate offset X/Y" to 0.  This results in
> incorrect rendering to mipmapped depth textures, but that seems like a
> reasonable stopgap while we figure out a better solution.
> 
> (Note that we have only ever observed this GPU hang on Gen6 when HiZ
> is enabled, so another possible stopgap would be to disable HiZ).
> 
> Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at
> texture sizes that are not powers of 2.
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c |   36 ++++++++++++++++++++++++++++
>  src/mesa/drivers/dri/i965/gen6_hiz.c       |   18 ++++++++++++++
>  2 files changed, 54 insertions(+), 0 deletions(-)

This should cause some nasty rendering if anyone uses mipmapped npot
depth textures. But I'm happy living with this workaround until we see a realworld
app that suffers from it.

For pot depth textures, this should cause rendering bugs at only tiny miplevels.
And I'm happy living with that as long it fixes GPU hangs.

Again, until we find a conformance test failure or a nasty rendering artifacts
in a real app, let's postpone on fixing the rendering bugs caused by this workaround.

Reviewed-by: Chad Verace <chad.versace at linux.intel.com>