[Mesa-dev] [PATCH 3/3] llvmpipe: Handle ISSG.

[Olivier Galibert]

Signed-off-by: Olivier Galibert <galibert at pobox.com>
---
 src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c |   13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index 0a43445..34f6c58 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -1113,6 +1113,18 @@ islt_emit_cpu(
    iset_emit_cpu(action, bld_base, emit_data, PIPE_FUNC_LESS);
 }
 
+/* TGSI_OPCODE_SSG (CPU Only) */
+
+static void
+issg_emit_cpu(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   emit_data->output[emit_data->chan] = lp_build_sgn(&bld_base->int_bld,
+                                                       emit_data->args[0]);
+}
+
 /* TGSI_OPCODE_LG2 (CPU Only) */
 static void
 lg2_emit_cpu(
@@ -1561,6 +1573,7 @@ lp_set_default_actions_cpu(
    bld_base->op_actions[TGSI_OPCODE_ISGE].emit = isge_emit_cpu;
    bld_base->op_actions[TGSI_OPCODE_ISHR].emit = ishr_emit_cpu;
    bld_base->op_actions[TGSI_OPCODE_ISLT].emit = islt_emit_cpu;
+   bld_base->op_actions[TGSI_OPCODE_ISSG].emit = issg_emit_cpu;
 
    bld_base->op_actions[TGSI_OPCODE_LG2].emit = lg2_emit_cpu;
    bld_base->op_actions[TGSI_OPCODE_LOG].emit = log_emit_cpu;
-- 
1.7.10.280.gaa39