[Mesa-dev] [PATCH 07/15] i965/blorp: Use 16 pixel dispatch on Gen7 when there is a WM program.

[Chad Versace]

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On 05/11/2012 11:03 AM, Paul Berry wrote:
> When executing a blorp operation on Gen7 that does not need a WM
> program (i.e. a HiZ operation), we use 32-pixel dispatch mode because
> it's faster.  However, when executing a blorp operation that does need
> a WM program, we need to use 16-pixel dispatch, because blorp WM
> programs are compiled assuming 16-pixel dispatch.
> ---
>  src/mesa/drivers/dri/i965/gen7_blorp.cpp |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> index dee342f..97289bb 100644
> --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> @@ -453,7 +453,13 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
>  
>     dw2 = dw4 = dw5 = 0;
>     dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
> -   dw4 |= GEN7_PS_32_DISPATCH_ENABLE;
> +   if (prog_data) {
> +      /* Program has been compiled for 16-pixel dispatch */
> +      dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
> +   } else {
> +      /* No program, so we can safely dispatch up to 32 pixels at a time */
> +      dw4 |= GEN7_PS_32_DISPATCH_ENABLE;
> +   }
>     if (intel->is_haswell)
>        dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
>     if (params->use_wm_prog) {


This is
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>.

I don't like that the dispatch width is implicit knowledge throughout the
code. But, I see that in gen7_wm_state.c that we use similiar logic. Blargh.
It would be nice to see the implicit knowledge made explicit, but that task
is for another day.
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