[Mesa-dev] [PATCH 11/12] i965/gen7: Add CC vieport setup to blorp code.

[Ian Romanick]

s/vieport/viewport/ in the commit message,

Does GEN6 need similar treatment?

On 05/22/2012 10:21 AM, Eric Anholt wrote:
> When doing fast clears, a fulsim warning said that the batch was being
> emitted without the viewport set up.  This could potentially have been
> a problem if some other app set the viewport to a range other than the
> [0,1] we want.
> ---
>   src/mesa/drivers/dri/i965/gen7_blorp.cpp |   21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> index 7ef0d36..4cad966 100644
> --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> @@ -110,6 +110,26 @@ gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
>      ADVANCE_BATCH();
>   }
>
> +static void
> +gen7_blorp_emit_cc_viewport(struct brw_context *brw,
> +			    const brw_blorp_params *params)
> +{
> +   struct intel_context *intel =&brw->intel;
> +   struct brw_cc_viewport *ccv;
> +   uint32_t cc_vp_offset;
> +
> +   ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
> +						   sizeof(*ccv), 32,
> +						&cc_vp_offset);
> +   ccv->min_depth = 0.0;
> +   ccv->max_depth = 1.0;
> +
> +   BEGIN_BATCH(2);
> +   OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC<<  16 | (2 - 2));
> +   OUT_BATCH(cc_vp_offset);
> +   ADVANCE_BATCH();
> +}
> +
>
>   /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
>    *
> @@ -765,6 +785,7 @@ gen7_blorp_exec(struct intel_context *intel,
>         gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
>      }
>      gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
> +   gen7_blorp_emit_cc_viewport(brw, params);
>
>      if (params->depth.mt)
>         gen7_blorp_emit_depth_stencil_config(brw, params);