[Mesa-dev] help
Westermann Fu
snail_314 at hotmail.com
Fri May 25 05:11:59 PDT 2012
-----Original Message-----
From: mesa-dev-request at lists.freedesktop.org
Sent: 25 May 2012 09:32:33 GMT
To: mesa-dev at lists.freedesktop.org
Subject: mesa-dev Digest, Vol 26, Issue 165
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Today's Topics:
1. [PATCH 1/7] r600g: add RECIP_INT, PRED_SETE_INT to
r600_bytecode_get_num_operands (Vadim Girlin)
2. [PATCH 2/7] radeon/llvm/loader: convert hardcoded gpu name to
option (Vadim Girlin)
3. [PATCH 3/7] radeon/llvm: fix opcode for RECIP_UINT_r600
(Vadim Girlin)
4. [PATCH 4/7] radeon/llvm: fix sampler index in llvm_emit_tex
(Vadim Girlin)
5. [PATCH 5/7] radeon/llvm: prepare to revert the round mode
state to default (Vadim Girlin)
6. [PATCH 6/7] radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT
instructions (Vadim Girlin)
7. [PATCH 7/7] Revert "r600g: set round_mode to truncate and get
rid of tgsi_f2i on evergreen" (Vadim Girlin)
----------------------------------------------------------------------
Message: 1
Date: Fri, 25 May 2012 13:26:01 +0400
From: Vadim Girlin <vadimgirlin at gmail.com>
Subject: [Mesa-dev] [PATCH 1/7] r600g: add RECIP_INT, PRED_SETE_INT to
r600_bytecode_get_num_operands
To: mesa-dev at lists.freedesktop.org
Message-ID: <1337937967-24175-1-git-send-email-vadimgirlin at gmail.com>
Content-Type: text/plain; charset=UTF-8
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50315
Tested-by: Kai Wasserb?ch <kai at dev.carbon-project.org>
Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
---
src/gallium/drivers/r600/r600_asm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index b73bbb3..b0cda3a 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -80,6 +80,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
@@ -103,6 +104,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode *
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
--
1.7.10.2
------------------------------
Message: 2
Date: Fri, 25 May 2012 13:26:02 +0400
From: Vadim Girlin <vadimgirlin at gmail.com>
Subject: [Mesa-dev] [PATCH 2/7] radeon/llvm/loader: convert hardcoded
gpu name to option
To: mesa-dev at lists.freedesktop.org
Message-ID: <1337937967-24175-2-git-send-email-vadimgirlin at gmail.com>
Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
---
src/gallium/drivers/radeon/loader.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/loader.cpp b/src/gallium/drivers/radeon/loader.cpp
index 79348d5..3ea8cd8 100644
--- a/src/gallium/drivers/radeon/loader.cpp
+++ b/src/gallium/drivers/radeon/loader.cpp
@@ -15,7 +15,8 @@ using namespace llvm;
static cl::opt<std::string>
InputFilename(cl::Positional, cl::desc("<input bitcode>"), cl::init("-"));
-
+static cl::opt<std::string>
+TargetGPUName("gpu", cl::desc("target gpu name"), cl::value_desc("gpu_name"));
int main(int argc, char ** argv)
{
@@ -30,5 +31,5 @@ int main(int argc, char ** argv)
Module * mod = M.get();
- radeon_llvm_compile(wrap(mod), &bytes, &byte_count, "redwood", 1);
+ radeon_llvm_compile(wrap(mod), &bytes, &byte_count, TargetGPUName.c_str(), 1);
}
--
1.7.10.2
------------------------------
Message: 3
Date: Fri, 25 May 2012 13:26:03 +0400
From: Vadim Girlin <vadimgirlin at gmail.com>
Subject: [Mesa-dev] [PATCH 3/7] radeon/llvm: fix opcode for
RECIP_UINT_r600
To: mesa-dev at lists.freedesktop.org
Message-ID: <1337937967-24175-3-git-send-email-vadimgirlin at gmail.com>
Content-Type: text/plain; charset=UTF-8
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50312
Tested-by: Kai Wasserb?ch <kai at dev.carbon-project.org>
Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
---
src/gallium/drivers/radeon/R600Instructions.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index b56d03c..88a03ab 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -749,7 +749,7 @@ let Predicates = [isR600] in {
def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
- def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>;
+ def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
def DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
--
1.7.10.2
------------------------------
Message: 4
Date: Fri, 25 May 2012 13:26:04 +0400
From: Vadim Girlin <vadimgirlin at gmail.com>
Subject: [Mesa-dev] [PATCH 4/7] radeon/llvm: fix sampler index in
llvm_emit_tex
To: mesa-dev at lists.freedesktop.org
Message-ID: <1337937967-24175-4-git-send-email-vadimgirlin at gmail.com>
Sampler index isn't a second source operand for some tgsi texture
instructions.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50230
Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
---
src/gallium/drivers/r600/r600_llvm.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_llvm.c b/src/gallium/drivers/r600/r600_llvm.c
index 2ca838f..5e073e0 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -144,15 +144,17 @@ static void llvm_emit_tex(
{
struct gallivm_state * gallivm = bld_base->base.gallivm;
LLVMValueRef args[6];
- unsigned c;
+ unsigned c, sampler_src;
assert(emit_data->arg_count + 2 <= Elements(args));
for (c = 0; c < emit_data->arg_count; ++c)
args[c] = emit_data->args[c];
+ sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;
+
args[c++] = lp_build_const_int32(gallivm,
- emit_data->inst->Src[1].Register.Index);
+ emit_data->inst->Src[sampler_src].Register.Index);
args[c++] = lp_build_const_int32(gallivm,
emit_data->inst->Texture.Texture);
--
1.7.10.2
------------------------------
Message: 5
Date: Fri, 25 May 2012 13:26:05 +0400
From: Vadim Girlin <vadimgirlin at gmail.com>
Subject: [Mesa-dev] [PATCH 5/7] radeon/llvm: prepare to revert the
round mode state to default
To: mesa-dev at lists.freedesktop.org
Message-ID: <1337937967-24175-5-git-send-email-vadimgirlin at gmail.com>
Use TRUNC before FLT_TO_INT on evergreen/cayman.
Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
---
src/gallium/drivers/radeon/R600Instructions.td | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 88a03ab..04f49cd 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -901,7 +901,6 @@ class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
def CNDGT_eg : CNDGT_Common<0x1A>;
def CNDGE_eg : CNDGE_Common<0x1B>;
def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
- def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>;
def EXP_IEEE_eg : EXP_IEEE_Common<0x81>;
def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
def LOG_IEEE_eg : LOG_IEEE_Common<0x83>;
@@ -916,7 +915,6 @@ class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
def MULLO_UINT_eg : MULLO_UINT_Common<0x91>;
def MULHI_UINT_eg : MULHI_UINT_Common<0x92>;
def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
- def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
def DOT4_eg : DOT4_Common<0xBE>;
def CUBE_eg : CUBE_Common<0xC0>;
@@ -928,6 +926,15 @@ class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
+ def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
+ let Pattern = [];
+ }
+
+ def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
+
+ def : Pat<(fp_to_sint R600_Reg32:$src),
+ (FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
+
}
let Predicates = [isCayman] in {
--
1.7.10.2
------------------------------
Message: 6
Date: Fri, 25 May 2012 13:26:06 +0400
From: Vadim Girlin <vadimgirlin at gmail.com>
Subject: [Mesa-dev] [PATCH 6/7] radeon/llvm: add FLT_TO_UINT,
UINT_TO_FLT instructions
To: mesa-dev at lists.freedesktop.org
Message-ID: <1337937967-24175-6-git-send-email-vadimgirlin at gmail.com>
Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
---
src/gallium/drivers/radeon/R600Instructions.td | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 04f49cd..b6b9fe0 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -618,6 +618,16 @@ class INT_TO_FLT_Common <bits<32> inst> : R600_1OP <
[(set R600_Reg32:$dst, (sint_to_fp R600_Reg32:$src))]
>;
+class FLT_TO_UINT_Common <bits<32> inst> : R600_1OP <
+ inst, "FLT_TO_UINT",
+ [(set R600_Reg32:$dst, (fp_to_uint R600_Reg32:$src))]
+>;
+
+class UINT_TO_FLT_Common <bits<32> inst> : R600_1OP <
+ inst, "UINT_TO_FLT",
+ [(set R600_Reg32:$dst, (uint_to_fp R600_Reg32:$src))]
+>;
+
class LOG_CLAMPED_Common <bits<32> inst> : R600_1OP <
inst, "LOG_CLAMPED",
[]
@@ -740,6 +750,8 @@ let Predicates = [isR600] in {
def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>;
def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>;
def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>;
+ def FLT_TO_UINT_r600 : FLT_TO_UINT_Common<0x79>;
+ def UINT_TO_FLT_r600 : UINT_TO_FLT_Common<0x6d>;
def SIN_r600 : SIN_Common<0x6E>;
def COS_r600 : COS_Common<0x6F>;
def ASHR_r600 : ASHR_Common<0x70>;
@@ -932,9 +944,17 @@ class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
+ def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
+ let Pattern = [];
+ }
+
+ def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>;
+
def : Pat<(fp_to_sint R600_Reg32:$src),
(FLT_TO_INT_eg (TRUNC R600_Reg32:$src))>;
+ def : Pat<(fp_to_uint R600_Reg32:$src),
+ (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
}
let Predicates = [isCayman] in {
--
1.7.10.2
------------------------------
Message: 7
Date: Fri, 25 May 2012 13:26:07 +0400
From: Vadim Girlin <vadimgirlin at gmail.com>
Subject: [Mesa-dev] [PATCH 7/7] Revert "r600g: set round_mode to
truncate and get rid of tgsi_f2i on evergreen"
To: mesa-dev at lists.freedesktop.org
Message-ID: <1337937967-24175-7-git-send-email-vadimgirlin at gmail.com>
This reverts commit 60bf0f05b472e66bf1175fcec7a274dab6f7e2a3.
It seems round_mode behaves differently in some cases depending on the
instruction/slot. Reverting it for now.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=50232
Signed-off-by: Vadim Girlin <vadimgirlin at gmail.com>
---
src/gallium/drivers/r600/evergreen_state.c | 8 ++---
src/gallium/drivers/r600/r600_shader.c | 54 ++++++++++++++++++++++++++--
2 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index c28eeab..ec0afe5 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2027,8 +2027,8 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
- r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
- r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
+ r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+ r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
@@ -2512,8 +2512,8 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
- r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
- r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_TO_ZERO));
+ r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
+ r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index cd78104..dc208b9 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3306,6 +3306,56 @@ static int tgsi_imod(struct r600_shader_ctx *ctx)
return tgsi_divmod(ctx, 1, 1);
}
+
+static int tgsi_f2i(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int i, r;
+ unsigned write_mask = inst->Dst[0].Register.WriteMask;
+ int last_inst = tgsi_last_instruction(write_mask);
+
+ for (i = 0; i < 4; i++) {
+ if (!(write_mask & (1<<i)))
+ continue;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC);
+
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
+ if (i == last_inst)
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+
+ for (i = 0; i < 4; i++) {
+ if (!(write_mask & (1<<i)))
+ continue;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.inst = ctx->inst_info->r600_opcode;
+
+ tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+
+ alu.src[0].sel = ctx->temp_reg;
+ alu.src[0].chan = i;
+
+ if (i == last_inst)
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+
+ return 0;
+}
+
static int tgsi_iabs(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -5368,7 +5418,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
{TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
/* gap */
{118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
- {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2},
+ {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_f2i},
{TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
{TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
{TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
@@ -5376,7 +5426,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
{TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
{TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
{TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
- {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2_trans},
+ {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_f2i},
{TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
{TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
{TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
--
1.7.10.2
------------------------------
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