[Mesa-dev] [PATCH] i965/vs: Add a comment about writemasking on scratch writes.

[Kenneth Graunke]

The OWord Dual Block Write message doesn't have a response length, so it
was surprising to a non-null destination register in the disassembly.
Not only that, but seeing g0 was especially confusing, as writing to g0
would destroy critical payload information that's needed for most SEND
messages.

I figured it would be worth adding a comment indicating the destination
register doesn't matter, but the writemask does (and is why we don't use
the null register.)

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 72766a2..440db1d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2501,6 +2501,10 @@ vec4_visitor::emit_scratch_write(vec4_instruction *inst, int base_offset)
    temp.swizzle = BRW_SWIZZLE4(swizzles[0], swizzles[1],
                                swizzles[2], swizzles[3]);
 
+   /* Since there's no response length, it doesn't matter what register we
+    * specify here.  However, the SEND instruction does use the destination
+    * register's writemask to determine which channels to write.
+    */
    dst_reg dst = dst_reg(brw_writemask(brw_vec8_grf(0, 0),
 				       inst->dst.writemask));
    vec4_instruction *write = SCRATCH_WRITE(dst, temp, index);
-- 
1.8.0