[Mesa-dev] [PATCH 4/6] i965: fs: Add fixup for textureSize on Gen7

[Chris Forbes]

Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
---
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 0050252..1fff000 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1072,10 +1072,24 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
       }
       break;
    }
-   case ir_txs:
+   case ir_txs: {
       emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
       mlen += reg_width;
+
+      /* fixup #layers for cube arrays */
+      glsl_type const * type = ir->sampler->variable_referenced()->type;
+      if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
+            type->sampler_array) {
+         /* emit_math can't cope with immediates. */
+         fs_reg * imm = new (mem_ctx) fs_reg(this, glsl_type::ivec4_type);
+         emit(MOV(*imm, fs_reg(6)));
+
+         fs_reg depth = dst;
+         depth.reg_offset = 2;
+         emit_math(SHADER_OPCODE_INT_QUOTIENT, depth, depth, *imm);
+      }
       break;
+   }
    case ir_txf:
       /* It appears that the ld instruction used for txf does its
        * address bounds check before adding in the offset.  To work
-- 
1.8.0