[Mesa-dev] [PATCH 5/8] PowerPC: clear Altivec NJ bit

[Adhemerval Zanella]

Mostly PowerPC system sets the Altivec NJ bit to 1 so denormal number
are handled as 0. Initially it was a performance configuration, since
denormal handling tended to be costly. However it is not the case on
more recent PowerPC chips (POWER6 and onwards).

This patch enforces the clear of NJ bit in VSCR Altivec register so
denormal numbers are handles as expected by IEEE standards
(more information on PowerISA 2.06 - Section 6.3). This make the
half-float to float transformation and some rounding work correctly
on an Altivec enabled machine.

Any tips, advices, comments?


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