[Mesa-dev] [PATCH] i965/fp: Fix segfault on gen4 TXB instructions.

[Kenneth Graunke]

On 11/28/2012 11:46 AM, Eric Anholt wrote:
> The gen4 simd16 workaround looks at ir->type to determine how much
> storage to allocate for the simd16 value.  In fragment programs,
> texturing only ever returns float vec4s (unlike GLSL, which can also
> have scalar floats or vector integers).
> ---
>   src/mesa/drivers/dri/i965/brw_fs_fp.cpp |    2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
> index bb8cd9a..4be7779 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
> @@ -441,6 +441,8 @@ fs_visitor::emit_fragment_program_code()
>               break;
>            }
>
> +         ir->type = glsl_type::vec4_type;
> +
>            const glsl_type *coordinate_type;
>            switch (fpi->TexSrcTarget) {
>            case TEXTURE_1D_INDEX:

Setting this can only be a good thing.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>