[Mesa-dev] [PATCH V3 3/7] i965: fs: fix gen6 math operands in one place

[Chris Forbes]

Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
---
 src/mesa/drivers/dri/i965/brw_fs.cpp | 48 +++++++++++++++++-------------------
 1 file changed, 23 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index cc5a790..cdfa46f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -864,6 +864,25 @@ fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
    return reg;
 }
 
+static fs_reg fix_operand_for_gen6_math(fs_visitor * v, fs_reg src) {
+   /* Can't do hstride == 0 args on gen6 math, so expand it out. We
+    * might be able to do better by doing execsize = 1 math and then
+    * expanding that result out, but we would need to be careful with
+    * masking.
+    *
+    * The hardware ignores source modifiers (negate and abs) on math
+    * instructions, so we also move to a temp to set those up.
+    */
+   if (src.file == UNIFORM || src.abs || src.negate) {
+      fs_reg expanded = fs_reg(v, glsl_type::float_type);
+      expanded.type = src.type;
+      v->emit(BRW_OPCODE_MOV, expanded, src);
+      return expanded;
+   }
+   else
+      return src;
+}
+
 fs_inst *
 fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
 {
@@ -889,13 +908,8 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
     * Gen 6 hardware ignores source modifiers (negate and abs) on math
     * instructions, so we also move to a temp to set those up.
     */
-   if (intel->gen == 6 && (src.file == UNIFORM ||
-			   src.abs ||
-			   src.negate)) {
-      fs_reg expanded = fs_reg(this, glsl_type::float_type);
-      emit(BRW_OPCODE_MOV, expanded, src);
-      src = expanded;
-   }
+   if (intel->gen == 6)
+      src = fix_operand_for_gen6_math(this, src);
 
    fs_inst *inst = emit(opcode, dst, src);
 
@@ -926,24 +940,8 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
    if (intel->gen >= 7) {
       inst = emit(opcode, dst, src0, src1);
    } else if (intel->gen == 6) {
-      /* Can't do hstride == 0 args to gen6 math, so expand it out.
-       *
-       * The hardware ignores source modifiers (negate and abs) on math
-       * instructions, so we also move to a temp to set those up.
-       */
-      if (src0.file == UNIFORM || src0.abs || src0.negate) {
-	 fs_reg expanded = fs_reg(this, glsl_type::float_type);
-	 expanded.type = src0.type;
-	 emit(BRW_OPCODE_MOV, expanded, src0);
-	 src0 = expanded;
-      }
-
-      if (src1.file == UNIFORM || src1.abs || src1.negate) {
-	 fs_reg expanded = fs_reg(this, glsl_type::float_type);
-	 expanded.type = src1.type;
-	 emit(BRW_OPCODE_MOV, expanded, src1);
-	 src1 = expanded;
-      }
+      src0 = fix_operand_for_gen6_math(this, src0);
+      src1 = fix_operand_for_gen6_math(this, src1);
 
       inst = emit(opcode, dst, src0, src1);
    } else {
-- 
1.8.0.1