[Mesa-dev] [PATCH 10/11] i965/vs: Simplify the scratch write handling and emit less code.

[Eric Anholt]

Kenneth Graunke <kenneth at whitecape.org> writes:

> On 10/04/2012 04:07 PM, Eric Anholt wrote:
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
>> index 5529794..79966e8 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
>> @@ -346,16 +346,7 @@ vec4_visitor::spill_reg(int spill_reg_nr)
>>         }
>>
>>         if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) {
>> -         dst_reg spill_reg = inst->dst;
>> -         inst->dst.reg = virtual_grf_alloc(1, 4);
>> -
>> -         /* We don't want a swizzle when reading from the source; read the
>> -          * whole register and use spill_reg's writemask to select which
>> -          * channels to write.
>> -          */
>> -         src_reg temp = src_reg(inst->dst);
>> -         temp.swizzle = BRW_SWIZZLE_XYZW;
>
> I don't understand how you can remove this.  You need to write out 
> inst->dst, but non-swizzled.  (Otherwise you re-swizzle your swizzles 
> and get the wrong channels...)
>
> Enable the "Go spill everything" debugging on brw_vec4_emit.cpp:817 and 
> then run:
>
> ./bin/shader_runner tests/shaders/glsl-vs-masked-cos.shader_test -auto
>
> Your patch causes an assertion failure, which is a regression:
> brw_eu_emit.c:1672: brw_math: Assertion `dest.file == 1' failed.

Updated branch is on vs-more-spill of my tree.  Lots more dumping code I
need to clean up and push.

That assertion was unrelated -- I was trying to math into a MRF, which
we assert you can't do (actually not true as of gen7, because MRFs are
GRFs).  But the test still broke after the initial fix with my swizzle
change.

I've now fixed up that failure too, but now I've got failure with
spill-everything in fs-varying-array-mat4-index-rd.shader_test and a few
others.  I think I've hit my limit of looking at shader dumps today.
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