[Mesa-dev] [PATCH 04/27] intel: Enable the support for GL_COMPRESSED_RGB8_ETC2 textures
Anuj Phogat
anuj.phogat at gmail.com
Fri Oct 19 16:28:39 PDT 2012
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 ++
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 59 ++++++++++++++++++++++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 14 +++--
3 files changed, 72 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 582e239..d3af2ce 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -557,6 +557,11 @@ brw_init_surface_formats(struct brw_context *brw)
* during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc1.
*/
ctx->TextureFormatSupported[MESA_FORMAT_ETC1_RGB8] = true;
+
+ /* On hardware that lacks support for ETC2, we map ETC2 to RGBX
+ * during glCompressedTexImage2D(). See intel_mipmap_tree::wraps_etc2.
+ */
+ ctx->TextureFormatSupported[MESA_FORMAT_ETC2_RGB8] = true;
}
bool
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 556a82f..61ff2db 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -200,6 +200,7 @@ intel_miptree_create(struct intel_context *intel,
uint32_t tiling = I915_TILING_NONE;
GLenum base_format;
bool wraps_etc1 = false;
+ bool wraps_etc2 = false;
GLuint total_width, total_height;
if (format == MESA_FORMAT_ETC1_RGB8) {
@@ -207,6 +208,11 @@ intel_miptree_create(struct intel_context *intel,
wraps_etc1 = true;
}
+ if (format == MESA_FORMAT_ETC2_RGB8) {
+ format = MESA_FORMAT_RGBX8888_REV;
+ wraps_etc2 = true;
+ }
+
base_format = _mesa_get_format_base_format(format);
if (intel->use_texture_tiling && !_mesa_is_format_compressed(format)) {
@@ -258,6 +264,7 @@ intel_miptree_create(struct intel_context *intel,
}
mt->wraps_etc1 = wraps_etc1;
+ mt->wraps_etc2 = wraps_etc2;
mt->region = intel_region_alloc(intel->intelScreen,
tiling,
mt->cpp,
@@ -1267,6 +1274,54 @@ intel_miptree_unmap_s8(struct intel_context *intel,
}
static void
+intel_miptree_map_etc2(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level,
+ unsigned int slice)
+{
+ /* For justification of these invariants,
+ * see intel_mipmap_tree:wraps_etc2.
+ */
+ assert(mt->wraps_etc2);
+ assert(mt->format == MESA_FORMAT_RGBX8888_REV);
+
+ /* intel_miptree_map_etc2() can be called from glCompressedTexImage2D
+ * and CompressedTexSubImage2D. Hence the assertions below hold.
+ */
+ assert(map->mode & GL_MAP_WRITE_BIT);
+ assert(map->mode & GL_MAP_INVALIDATE_RANGE_BIT);
+
+ map->stride = _mesa_format_row_stride(MESA_FORMAT_ETC2_RGB8, map->w);
+ map->buffer = malloc(_mesa_format_image_size(MESA_FORMAT_ETC2_RGB8,
+ map->w, map->h, 1));
+ map->ptr = map->buffer;
+}
+
+static void
+intel_miptree_unmap_etc2(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ struct intel_miptree_map *map,
+ unsigned int level,
+ unsigned int slice)
+{
+ uint32_t image_x;
+ uint32_t image_y;
+ intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y);
+
+ uint8_t *xbgr = intel_region_map(intel, mt->region, map->mode)
+ + image_y * mt->region->pitch * mt->region->cpp
+ + image_x * mt->region->cpp;
+
+ _mesa_unpack_etc2_format(xbgr, mt->region->pitch * mt->region->cpp,
+ map->ptr, map->stride,
+ map->w, map->h);
+
+ intel_region_unmap(intel, mt->region);
+ free(map->buffer);
+}
+
+static void
intel_miptree_map_etc1(struct intel_context *intel,
struct intel_mipmap_tree *mt,
struct intel_miptree_map *map,
@@ -1538,6 +1593,8 @@ intel_miptree_map_singlesample(struct intel_context *intel,
intel_miptree_map_s8(intel, mt, map, level, slice);
} else if (mt->wraps_etc1) {
intel_miptree_map_etc1(intel, mt, map, level, slice);
+ } else if (mt->wraps_etc2) {
+ intel_miptree_map_etc2(intel, mt, map, level, slice);
} else if (mt->stencil_mt) {
intel_miptree_map_depthstencil(intel, mt, map, level, slice);
} else if (intel->has_llc &&
@@ -1576,6 +1633,8 @@ intel_miptree_unmap_singlesample(struct intel_context *intel,
intel_miptree_unmap_s8(intel, mt, map, level, slice);
} else if (mt->wraps_etc1) {
intel_miptree_unmap_etc1(intel, mt, map, level, slice);
+ } else if (mt->wraps_etc2) {
+ intel_miptree_unmap_etc2(intel, mt, map, level, slice);
} else if (mt->stencil_mt) {
intel_miptree_unmap_depthstencil(intel, mt, map, level, slice);
} else if (map->bo) {
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 0d0e757..a1121e7 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -351,16 +351,18 @@ struct intel_mipmap_tree
struct intel_mipmap_tree *mcs_mt;
/**
- * \brief The miptree contains RGBX data that was originally ETC1 data.
+ * \brief The miptree contains RGBX data that was originally ETC1/ETC2 data.
*
- * On hardware that lacks support for ETC1 textures, we do the
- * following on calls to glCompressedTexImage2D(GL_ETC1_RGB8_OES):
+ * On hardware that lacks support for ETC1 textures, we do the following
+ * on calls to glCompressedTexImage2D() with format GL_ETC1_RGB8_OES or
+ * GL_COMPRESSED_RGB_ETC2:
* 1. Create a miptree whose format is MESA_FORMAT_RGBX8888_REV with
- * the wraps_etc1 flag set.
- * 2. Translate the ETC1 data into RGBX.
- * 3. Store the RGBX data into the miptree and discard the ETC1 data.
+ * the wraps_etc1 / wraps_etc2 flag set.
+ * 2. Translate the ETC1 / ETC2 data into RGBX.
+ * 3. Store the RGBX data into the miptree and discard the ETC1/ETC2 data.
*/
bool wraps_etc1;
+ bool wraps_etc2;
/* These are also refcounted:
*/
--
1.7.7.6
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