[Mesa-dev] [PATCH 5/6] i965: emit w/a for packed attribute formats in VS

[Chris Forbes]

Implements BGRA swizzle, sign recovery, and normalization
as required by ARB_vertex_type_10_10_10_2_rev.

This patch only adds the support to the "old" VS backend;
this is what is tested by the piglit tests. Port to the new
VS backend is still to come.

Normalization is sloppy, and will be revisited for final version.

Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 49 +++++++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index a4742c7..bfb617a 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1581,26 +1581,71 @@ accumulator_contains(struct brw_vs_compile *c, struct brw_reg val)
    }
 }
 
+/* apply various attribute format workarounds */
 static void
 brw_vs_apply_attrib_wa(struct brw_vs_compile *c)
 {
    struct brw_compile *p = &c->func;
+   struct brw_reg shift_tmp;
+   struct brw_reg shift_tmp_ud = retype(shift_tmp, BRW_REGISTER_TYPE_UD);
    int i;
+   int any_sign_recovery = 0;
+
+   for (i = 0; i < VERT_ATTRIB_MAX; i++)
+      if (c->prog_data.inputs_read & BITFIELD64_BIT(i))
+         if (c->key.gl_attrib_wa_flags[i] & BRW_ATTRIB_WA_SIGN)
+            any_sign_recovery = 1;
+
+   /* set up the shift value for sign recovery if any attribs needed it */
+   if (any_sign_recovery) {
+      shift_tmp = get_tmp(c);
+      brw_MOV(p, brw_writemask(shift_tmp_ud, WRITEMASK_XYZ), brw_imm_ud(22));
+      brw_MOV(p, brw_writemask(shift_tmp_ud, WRITEMASK_W), brw_imm_ud(30));
+   }
 
    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
       uint8_t wa_flags = c->key.gl_attrib_wa_flags[i];
+      struct brw_reg reg = c->regs[PROGRAM_INPUT][i];
+      struct brw_reg reg_d = retype(reg, BRW_REGISTER_TYPE_D);
+      struct brw_reg reg_ud = retype(reg, BRW_REGISTER_TYPE_UD);
+
       if (!(c->prog_data.inputs_read & BITFIELD64_BIT(i)))
          continue;
 
       if (wa_flags & BRW_ATTRIB_WA_COMPONENTS) {
-         struct brw_reg reg = c->regs[PROGRAM_INPUT][i];
          brw_MUL(p,
             brw_writemask(reg, (1 << (wa_flags & BRW_ATTRIB_WA_COMPONENTS)) - 1),
             reg, brw_imm_f(1.0 / 65536.0));
       }
 
-      /* TODO: emit other packed vertex attrib w/a shader code here. */
+      if (wa_flags & BRW_ATTRIB_WA_SIGN) {
+         brw_SHL(p, reg_ud, reg_ud, shift_tmp_ud);
+         brw_ASR(p, reg_d, reg_d, shift_tmp_ud);
+      }
+
+      if (wa_flags & BRW_ATTRIB_WA_BGRA) {
+         brw_MOV(p, reg_ud, brw_swizzle(reg_ud, 2,1,0,3));
+      }
+
+      if (wa_flags & BRW_ATTRIB_WA_NORMALIZE) {
+         /* normalize according to GL 3.2 spec eqn 2.2, 2.3? this is sloppy. */
+         brw_MOV(p, reg, (wa_flags & BRW_ATTRIB_WA_SIGN) ? reg_d : reg_ud);
+         brw_MUL(p, brw_writemask(reg, WRITEMASK_XYZ), reg,
+               (wa_flags & BRW_ATTRIB_WA_SIGN) ? brw_imm_f(1.0 / 512.0)
+                  : brw_imm_f(1.0 / 1024.0));
+         if (~wa_flags & BRW_ATTRIB_WA_SIGN)
+            brw_MUL(p, brw_writemask(reg, WRITEMASK_W), reg,
+               brw_imm_f(1.0 / 3.0));
+      }
+
+      if (wa_flags & BRW_ATTRIB_WA_SCALE) {
+         /* just convert from int to float */
+         brw_MOV(p, reg, (wa_flags & BRW_ATTRIB_WA_SIGN) ? reg_d : reg_ud);
+      }
    }
+
+   if (any_sign_recovery)
+      release_tmp(c, shift_tmp_ud);
 }
 
 /* Emit the vertex program instructions here.
-- 
1.7.12.4