[Mesa-dev] [PATCH] AMDGPU: Only allow SGPR for the first operand of SI VOP3 instructions.

[Michel Dänzer]

From: Michel Dänzer <michel.daenzer at amd.com>

This is technically too strict: While a VOP3 instruction can only use one SGPR,
it can be used for any operand, even for several operands at the same. But for
now this is a simple solution which fixes the problem (e.g. causing broken
linear fog with radeonsi) at little extra cost (in the form of V_MOV_* from
SGPR to VGPR).

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
 lib/Target/AMDGPU/SIInstrFormats.td |    4 ++--
 lib/Target/AMDGPU/SIInstructions.td |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/lib/Target/AMDGPU/SIInstrFormats.td b/lib/Target/AMDGPU/SIInstrFormats.td
index 97d54ac..aea3b5a 100644
--- a/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/lib/Target/AMDGPU/SIInstrFormats.td
@@ -35,10 +35,10 @@ class VOP3_1_32 <bits<9> op, string opName, list<dag> pattern>
   : VOP3b_2IN <op, opName, SReg_1, AllReg_32, VReg_32, pattern>;
 
 class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
-  : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
+  : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
 
 class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
-  : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
+  : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
 
 
 class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index cb94381..bdac6a4 100644
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -1249,8 +1249,8 @@ def : Pat <
 /**********   VOP3 Patterns    **********/
 /********** ================== **********/
 
-def : Pat <(f32 (IL_mad AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2)),
-           (V_MAD_LEGACY_F32 AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2,
+def : Pat <(f32 (IL_mad AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2)),
+           (V_MAD_LEGACY_F32 AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2,
             0, 0, 0, 0)>;
 
 } // End isSI predicate
-- 
1.7.10.4