[Mesa-dev] [PATCH 5/7] AMDGPU: Use SReg_1 class for SI_IF_(N)Z condition code operand.

[Michel Dänzer]

From: Michel Dänzer <michel.daenzer at amd.com>

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
 lib/Target/AMDGPU/SIInstructions.td |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index 980bf63..8b4245d 100644
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -1092,14 +1092,14 @@ let isBranch = 1, isTerminator = 1, mayLoad = 0, mayStore = 0,
                                                  hasSideEffects = 0 in {
 def SI_IF_NZ : InstSI <
   (outs),
-  (ins brtarget:$target, VCCReg:$vcc),
+  (ins brtarget:$target, SReg_1:$vcc),
   "SI_BRANCH_NZ",
-  [(IL_brcond bb:$target, VCCReg:$vcc)]
+  [(IL_brcond bb:$target, SReg_1:$vcc)]
 >;
 
 def SI_IF_Z : InstSI <
   (outs),
-  (ins brtarget:$target, VCCReg:$vcc),
+  (ins brtarget:$target, SReg_1:$vcc),
   "SI_BRANCH_Z",
   []
 >;
-- 
1.7.10.4