[Mesa-dev] [PATCH 1/7] AMDGPU: Use SReg_64RegClass for i64 register class on SI.

[Christian König]

Wow, a quite impressive step forward.

I'm not so deeply into the LLVM code, but apart from that it's:

Reviewed-by: Christian König <christian.koenig at amd.com>

On 30.10.2012 19:39, Michel Dänzer wrote:
> From: Tom Stellard <thomas.stellard at amd.com>
>
> Fixes invalid code being generated, trying to copy from VGPRs to SGPRs.
>
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
> ---
>   lib/Target/AMDGPU/SIISelLowering.cpp |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp
> index 1203069..c6f93d7 100644
> --- a/lib/Target/AMDGPU/SIISelLowering.cpp
> +++ b/lib/Target/AMDGPU/SIISelLowering.cpp
> @@ -31,7 +31,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
>     addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
>     addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
>     addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
> -  addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass);
> +  addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
>     addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass);
>     addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass);
>