[Mesa-dev] [PATCH 00/12] i965/blorp: Fix blits between miplevels other than zero.

[Paul Berry]

This patch series addresses a bug Eric Anholt and Chad Versace noticed
a few weeks ago: the blorp engine wasn't paying attention to miplevels
and layers; as a result, all blits were occuring on miplevel/layer
zero, regardless of which level and layer were bound to the
framebuffer.

Patch 01 fixes a longstanding bug in the allocation of mipmapped
stencil buffers, which caused us to sometimes allocate too small a
buffer, risking GPU hangs if the render to a region outside the
allocated buffer.  Although this is technically an independent bug, we
can't validate that the blits work correctly until we fix it.

Patches 02-07 fix blits for all buffers other than stencil buffers, by
threading the miplevel and layer through to the blorp functions and
using them to compute appropriate offsets into the buffers.

Patches 08-12 fix blits for stencil buffers, by making some important
corrections to the offsets and buffer sizes related to the fact that
stencil buffers are W-tiled.  Without these corrections we might
sometimes compute too large an offset when using stencil buffers,
risking GPU hangs if we blit data to a region outside the allocated
buffer.

Note: although blits between mipmapped stencil buffers are probably
very rare (they can only happen when blitting stencil data between
mipmapped depth/stencil buffers, something a reasonable app is
unlikely to need to do), I still believe it's wise to apply patches 01
and 08-12 to avoid GPU hangs.

I've marked the patches in this series as candidates for stable
release branches, since they fix blorp, which is new to Mesa 9.0.

To validate these fixes, I've expanded the piglit test
framebuffer-blit-levels to be able to test stencil buffers.  Those
patches should hit the piglit list soon.

[PATCH 01/12] i965/gen6+: Adjust stencil buffer size after computing miptree layout.
[PATCH 02/12] i965/blorp: Clarify why width/height must be adjusted for Gen6 IMS surfaces.
[PATCH 03/12] i965/blorp: Change gl_renderbuffer* params to intel_renderbuffer*.
[PATCH 04/12] i965/blorp: store surface width/height in brw_blorp_mip_info.
[PATCH 05/12] i965/blorp: store x and y offsets in brw_blorp_mip_info.
[PATCH 06/12] i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().
[PATCH 07/12] i965/blorp: Account for offsets when emitting SURFACE_STATE.
[PATCH 08/12] intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
[PATCH 09/12] intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
[PATCH 10/12] i965/blorp: don't reduce stencil alignment when multisampling.
[PATCH 11/12] i965/blorp: Reduce alignment restrictions for stencil blits.
[PATCH 12/12] i965/blorp: Fix offsets and width/height for stencil blits.