[Mesa-dev] [PATCH 09/12] intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
Paul Berry
stereotype441 at gmail.com
Wed Sep 5 12:17:32 PDT 2012
This patch modifies intel_region_get_aligned_offset() to make the
appropriate calculation when the blorp engine sets up a W-tiled
stencil buffer using a Y-tiled SURFACE_STATE.
NOTE: This is a candidate for stable release branches.
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_misc_state.c | 5 +++--
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 4 ++--
src/mesa/drivers/dri/i965/gen7_misc_state.c | 6 ++++--
src/mesa/drivers/dri/intel/intel_fbo.c | 2 +-
src/mesa/drivers/dri/intel/intel_regions.c | 18 ++++++++++++++++--
src/mesa/drivers/dri/intel/intel_regions.h | 2 +-
8 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index e81194e..b08ce07 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -136,7 +136,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
*tile_y = y_offset & mask_y;
return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
- y_offset & ~mask_y);
+ y_offset & ~mask_y,
+ map_stencil_as_y_tiled);
}
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 52926fb..6dfa08e 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -474,7 +474,7 @@ static void emit_depthbuffer(struct brw_context *brw)
offset = intel_region_get_aligned_offset(region,
draw_x & ~tile_mask_x,
- draw_y & ~tile_mask_y);
+ draw_y & ~tile_mask_y, false);
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
@@ -518,7 +518,8 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_region,
draw_x & ~tile_mask_x,
- (draw_y & ~tile_mask_y) / 2);
+ (draw_y & ~tile_mask_y) / 2,
+ false);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 3e0b80e..1f536bf 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -843,7 +843,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t offset =
intel_region_get_aligned_offset(params->depth.mt->region,
draw_x & ~tile_mask_x,
- draw_y & ~tile_mask_y);
+ draw_y & ~tile_mask_y, false);
/* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
* (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
@@ -896,7 +896,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_region,
draw_x & ~tile_mask_x,
- (draw_y & ~tile_mask_y) / 2);
+ (draw_y & ~tile_mask_y) / 2, false);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index b38fad9..d11bc5a 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -591,7 +591,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t offset =
intel_region_get_aligned_offset(params->depth.mt->region,
draw_x & ~tile_mask_x,
- draw_y & ~tile_mask_y);
+ draw_y & ~tile_mask_y, false);
/* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
* (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
@@ -640,7 +640,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_region,
draw_x & ~tile_mask_x,
- (draw_y & ~tile_mask_y) / 2);
+ (draw_y & ~tile_mask_y) / 2, false);
BEGIN_BATCH(3);
OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 9709b8e..1d22448 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -181,7 +181,8 @@ static void emit_depthbuffer(struct brw_context *brw)
offset = intel_region_get_aligned_offset(region,
draw_x & ~tile_mask_x,
- draw_y & ~tile_mask_y);
+ draw_y & ~tile_mask_y,
+ false);
assert(region->tiling == I915_TILING_Y);
@@ -215,7 +216,8 @@ static void emit_depthbuffer(struct brw_context *brw)
uint32_t hiz_offset =
intel_region_get_aligned_offset(hiz_mt->region,
draw_x & ~tile_mask_x,
- (draw_y & ~tile_mask_y) / 2);
+ (draw_y & ~tile_mask_y) / 2,
+ false);
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH(hiz_mt->region->pitch * hiz_mt->region->cpp - 1);
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index bd9548b..ba360c5 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -586,7 +586,7 @@ intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb,
*tile_x = irb->draw_x & mask_x;
*tile_y = irb->draw_y & mask_y;
return intel_region_get_aligned_offset(region, irb->draw_x & ~mask_x,
- irb->draw_y & ~mask_y);
+ irb->draw_y & ~mask_y, false);
}
/**
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 18402d6..7cb008c 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -437,12 +437,26 @@ intel_region_get_tile_masks(struct intel_region *region,
*/
uint32_t
intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
- uint32_t y)
+ uint32_t y, bool map_stencil_as_y_tiled)
{
int cpp = region->cpp;
uint32_t pitch = region->pitch * cpp;
+ uint32_t tiling = region->tiling;
+
+ if (map_stencil_as_y_tiled) {
+ tiling = I915_TILING_Y;
- switch (region->tiling) {
+ /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
+ * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
+ * the resulting region is twice the pitch of the original region, since
+ * each row in the Y-tiled view corresponds to two rows in the actual
+ * W-tiled surface. So we need to correct the pitch before computing
+ * the offsets.
+ */
+ pitch *= 2;
+ }
+
+ switch (tiling) {
default:
assert(false);
case I915_TILING_NONE:
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h b/src/mesa/drivers/dri/intel/intel_regions.h
index e259a1e..8737a6d 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.h
+++ b/src/mesa/drivers/dri/intel/intel_regions.h
@@ -140,7 +140,7 @@ intel_region_get_tile_masks(struct intel_region *region,
uint32_t
intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
- uint32_t y);
+ uint32_t y, bool map_stencil_as_y_tiled);
/**
* Used with images created with image_from_names
--
1.7.7.6
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