[Mesa-dev] [PATCH 1/4 v2] radeon/llvm: Extend SI EXEC register support.

[Michel Dänzer]

From: Michel Dänzer <michel.daenzer at amd.com>

Add 32 bit lo and hi variants, and binary encodings.

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---

v2: Make EXEC subclass SI_64, and pass in EXEC_LO and EXEC_HI as overlapping
sub-registers. Is this what you meant, Tom?

 src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp |    3 +++
 src/gallium/drivers/radeon/SIGenRegisterInfo.pl             |    6 ++++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
index c2b5e47..438d2ac 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -281,6 +281,9 @@ unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
 unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
   switch (reg) {
     case AMDGPU::M0: return 124;
+    case AMDGPU::EXEC: return 126;
+    case AMDGPU::EXEC_LO: return 126;
+    case AMDGPU::EXEC_HI: return 127;
     case AMDGPU::SREG_LIT_0: return 128;
     case AMDGPU::SI_LITERAL_CONSTANT: return 255;
     default: return getHWRegNum(reg);
diff --git a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
index e47fb56..3813eb5 100644
--- a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
+++ b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
@@ -88,7 +88,9 @@ class SGPR_256 <bits<8> num, string name, list<Register> subregs> :
     SI_256 <name, subregs>;
 
 def VCC : SIReg<"VCC">;
-def EXEC : SIReg<"EXEC">;
+def EXEC_LO : SIReg<"EXEC LO">;
+def EXEC_HI : SIReg<"EXEC HI">;
+def EXEC : SI_64<"EXEC", [EXEC_LO,EXEC_HI]>;
 def SCC : SIReg<"SCC">;
 def SREG_LIT_0 : SIReg <"S LIT 0">;
 def SI_LITERAL_CONSTANT : SIReg<"LITERAL CONSTANT">;
@@ -141,7 +143,7 @@ for (my $i = 0; $i < $VGPR_COUNT; $i++) {
 print <<STRING;
 
 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
-    (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX),  SREG_LIT_0, M0)
+    (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX),  SREG_LIT_0, M0, EXEC_LO, EXEC_HI)
 >;
 
 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
-- 
1.7.10.4