[Mesa-dev] [PATCH] r600g: order atom emission

[Jerome Glisse]

On Thu, Sep 6, 2012 at 6:20 AM, Dave Airlie <airlied at gmail.com> wrote:
> On Thu, Sep 6, 2012 at 5:21 PM, Philipp Klaus Krause <pkk at spth.de> wrote:
>> On 06.09.2012 07:35, j.glisse at gmail.com wrote:
>>> From: Jerome Glisse <jglisse at redhat.com>
>>>
>>> To avoid GPU lockup registers must be emited in a specific order
>>> (no kidding ...). This patch rework atom emission so order in which
>>> atom are emited in respect to each other is always the same. We
>>> don't have any informations on what is the correct order so order
>>> will need to be infered from fglrx command stream.
>>
>> Shouldn't this be stated in comments, so the next person who comes along
>> and makes a change in this code doesn't inadvertently change the order?
>
> Also a comment on what ordering matters most, like I suspect this is
> just hiding a real issue.
>
> Dave.

No it's not hiding an issue, afaict it's how the hw works. The hw do
what some amd document call states validations. So here is how i
understand how things happen and i can be completely wrong. Hw process
register write in order it receive them and to avoid postponing state
validation the hw do state validation while processing register. That
means if writing register A trigger state validation that use some
field of register B the hw might not redo state validation when
register B is latter written. ie only some register trigger the state
validation no matter on what they depends on. I believe state
validation is only use as pipeline optimization by the hw, so the hw
knows it can take some short cut. But in some rare case if short cut
are taken for wrong reasons we end up in GPU lockup.

No matter if my guess is right or wrong, i know for a fact that
register order is important in some situation, that's the hard bottom
line, no matter what is the reasons inside the hw.

This patch is far from having all the order right, it's just a first
step, i am atomizing everything and it's what needed to go forward
without regression.

Note that i have been told that in the r100/r200 days same issue came
up and registers needed to be written in some specific order (well
only some register matter but i doubt we have a good knowledge on
that).

Cheers,
Jerome