[Mesa-dev] [PATCH 01/12] i965/gen6+: Adjust stencil buffer size after computing miptree layout.

[Eric Anholt]

Paul Berry <stereotype441 at gmail.com> writes:

> Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which
> drm and the kernel are not aware of) we need to round up the width and
> height of a stencil buffer to multiples of the W-tile size (64x64)
> before allocating a stencil buffer.  Previously, we rounded up the
> size of the base miplevel, and then computed the miptree layout based
> on the rounded up size.  This was incorrect, because it meant that the
> total size of the miptree would not be properly W-tile aligned, and
> therefore we would not always allocate enough pages.
>
> (Note: even though the GL API doesn't allow creation of mipmapped
> stencil textures, it does allow mipmapping of a combined depth/stencil
> texture, and on Gen6+, a combined depth/stencil texture is internally
> implemented as a pair of separate depth and stencil buffers.)
>
> For example, on Sandy Bridge, when allocating a mipmapped stencil
> texture of size 128x128, we would first round up to the nearest
> multiple of 64x64 (causing no change to the size), and then compute
> the miptree layout (whose size worked out to 128x196).  Then we would
> request an allocation of 128*196 bytes (6.125 pages), causing 7 pages
> to be allocated to the texture.  However, the texture needs 8 pages,
> since each W-tile occupies a page, and it takes 2 W-tiles to cover a
> width of 128 and 4 W-tiles to cover a height of 196.
>
> This patch changes the order of operations so that the miptree layout
> is computed first and then the total size of the miptree is rounded up
> to be W-tile aligned.

I had a similar patch, so either variation gets my r-b.  (mt->total_*
are only used for communicating the size of the region to be requested,
so the alignment can be done in place)
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