[Mesa-dev] [PATCH 02/12] i965/blorp: Clarify why width/height must be adjusted for Gen6 IMS surfaces.

[Eric Anholt]

Paul Berry <stereotype441 at gmail.com> writes:

> Also add a clarifying comment for why the width/height doesn't need
> adjustment for Gen7.

> diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> index a65a975..ff11f3a 100644
> --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
> @@ -144,6 +144,11 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
>     uint32_t wm_surf_offset;
>     uint32_t width, height;
>     surface->get_miplevel_dims(&width, &height);
> +   /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_IMS for

Is that supposed to be s/IMS/UMS/?
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