[Mesa-dev] [PATCH 08/10] radeon/llvm: Add register encoding for VCC

[Tom Stellard]

From: Tom Stellard <thomas.stellard at amd.com>

---
 .../radeon/MCTargetDesc/SIMCCodeEmitter.cpp        |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
index 438d2ac..ca4b579 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -280,6 +280,7 @@ unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
 
 unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
   switch (reg) {
+    case AMDGPU::VCC: return 106;
     case AMDGPU::M0: return 124;
     case AMDGPU::EXEC: return 126;
     case AMDGPU::EXEC_LO: return 126;
-- 
1.7.3.4