[Mesa-dev] [PATCH 2/3] intel: Do temporary CPU maps of textures that are too big to GTT map.

[Daniel Vetter]

On Tue, Apr 02, 2013 at 06:46:32PM -0700, Eric Anholt wrote:
> This still fails, since 8192*4bpp == 32768, which is too big to use the
> blitter on.

Meh, I should take coffee first before doing reviews ...

Iirc on gen4+ for tiled src/dst the blt stride limit is 128k (since the
stride is supplied in dwords instead of bytes). Also, with the new
snoopable bo support in the kernel v3.7 you should be able to use the
blitter also on non-llc platforms (safe for i965g/gm, the hw is busted
there), which will cut away the clflushing when accessing the cpu maps.
-Daniel

> 
> Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/intel/intel_mipmap_tree.c |   21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> index ffdaec5..5e0cd61 100644
> --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> @@ -1703,6 +1703,23 @@ intel_miptree_map_singlesample(struct intel_context *intel,
>  {
>     struct intel_miptree_map *map;
>  
> +   /* Estimate the size of the mappable aperture into the GTT.  There's an
> +    * ioctl to get the whole GTT size, but not one to get the mappable subset.
> +    * It turns out it's basically always 256MB, though some ancient hardware
> +    * was smaller.
> +    */
> +   uint32_t gtt_size = 256 * 1024 * 1024;
> +   if (intel->gen == 2)
> +      gtt_size = 128 * 1024 * 1024;
> +
> +   /* We don't want to map two objects such that a memcpy between them would
> +    * just fault one mapping in and then the other over and over forever.  So
> +    * we would need to divide the GTT size by 2.  Additionally, some GTT is
> +    * taken up by things like the framebuffer and the ringbuffer and such, so
> +    * be more conservative.
> +    */
> +   uint32_t max_gtt_map_object_size = gtt_size / 4;
> +
>     assert(mt->num_samples <= 1);
>  
>     map = intel_miptree_attach_map(mt, level, slice, x, y, w, h, mode);
> @@ -1749,6 +1766,10 @@ intel_miptree_map_singlesample(struct intel_context *intel,
>              mt->region->tiling == I915_TILING_X &&
>              mt->region->pitch < 32768) {
>        intel_miptree_map_blit(intel, mt, map, level, slice);
> +   } else if (mt->region->tiling != I915_TILING_NONE &&
> +              mt->region->bo->size >= max_gtt_map_object_size) {
> +      assert(mt->region->pitch < 32768);
> +      intel_miptree_map_blit(intel, mt, map, level, slice);
>     } else {
>        intel_miptree_map_gtt(intel, mt, map, level, slice);
>     }
> -- 
> 1.7.10.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch