[Mesa-dev] [PATCH 1/2] i965/vs: Fix writemasks on pull constant offset setup.

[Eric Anholt]

When you src_reg(dst_reg(int_type)), you get a grf.xxxx (swizzle).  But if
you dst_reg(src_reg(int_type)), you get a grf.xyzw (writemask).  By going
the direction we did, we were writing more channels than were read, so we
wouldn't register coalesce the ADD or MUL.

Right now the MOV is still baked into the emit, but I'm about to fix it
for gen7.
---
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 8bd2fd8..ce07381 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2716,18 +2716,18 @@ vec4_visitor::get_pull_constant_offset(vec4_instruction *inst,
 				       src_reg *reladdr, int reg_offset)
 {
    if (reladdr) {
-      src_reg index = src_reg(this, glsl_type::int_type);
+      dst_reg index = dst_reg(this, glsl_type::int_type);
 
-      emit_before(inst, ADD(dst_reg(index), *reladdr, src_reg(reg_offset)));
+      emit_before(inst, ADD(index, *reladdr, src_reg(reg_offset)));
 
       /* Pre-gen6, the message header uses byte offsets instead of vec4
        * (16-byte) offset units.
        */
       if (intel->gen < 6) {
-	 emit_before(inst, MUL(dst_reg(index), index, src_reg(16)));
+	 emit_before(inst, MUL(index, src_reg(index), src_reg(16)));
       }
 
-      return index;
+      return src_reg(index);
    } else {
       int message_header_scale = intel->gen < 6 ? 16 : 1;
       return src_reg(reg_offset * message_header_scale);
-- 
1.7.10.4