[Mesa-dev] [PATCH 4/4] radeonsi: Handle new format for configuration values emitted by the LLVM backend

[Tom Stellard]

From: Tom Stellard <thomas.stellard at amd.com>

Instead of emitting configuration values (e.g. number of gprs used) in a
predefined order, the LLVM backend now emits these values in
register/value pairs.  The first dword contains the register address and
the second dword contians the value to write.
---
 src/gallium/drivers/radeonsi/radeonsi_shader.c | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 0aeecc2..78c1cf4 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -1175,9 +1175,29 @@ int si_pipe_shader_create(
 		}
 	}
 
-	shader->num_sgprs = util_le32_to_cpu(*(uint32_t*)binary.config);
-	shader->num_vgprs = util_le32_to_cpu(*(uint32_t*)(binary.config + 4));
-	shader->spi_ps_input_ena = util_le32_to_cpu(*(uint32_t*)(binary.config + 8));
+	/* XXX: We may be able to emit some of these values directly rather than
+	 * extracting fields to be emitted later.
+	 */
+	for (i = 0; i < binary.config_size; i+= 8) {
+		unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
+		unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
+		switch (reg) {
+		case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
+		case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
+		case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
+		case R_00B848_COMPUTE_PGM_RSRC1:
+			shader->num_sgprs = (G_00B028_SGPRS(value) * 8) + 1;
+			shader->num_vgprs = (G_00B028_VGPRS(value) * 4) + 1;
+			break;
+		case R_0286CC_SPI_PS_INPUT_ENA:
+			shader->spi_ps_input_ena = value;
+			break;
+		default:
+			fprintf(stderr, "Warning: Compiler emitted unknown "
+				"config register: 0x%x\n", reg);
+			break;
+		}
+	}
 
 	radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
 	tgsi_parse_free(&si_shader_ctx.parse);
-- 
1.8.1.5