[Mesa-dev] [PATCH 5/8] i965: Change signature of brw_get_depthstencil_tile_masks()

[Kenneth Graunke]

From: Chad Versace <chad.versace at linux.intel.com>

Add new parameters `depth_level` and `depth_layer`, which specify depth
miptree's slice of interest.  A following patch will pass the new
parameters through to intel_miptree_slice_has_hiz().

Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h    | 2 ++
 src/mesa/drivers/dri/i965/brw_misc_state.c | 7 ++++++-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp   | 5 ++++-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp   | 5 ++++-
 4 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index afcba46..541288d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1127,6 +1127,8 @@ bool brwCreateContext(int api,
  * brw_misc_state.c
  */
 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
+                                     uint32_t depth_level,
+                                     uint32_t depth_layer,
                                      struct intel_mipmap_tree *stencil_mt,
                                      uint32_t *out_tile_mask_x,
                                      uint32_t *out_tile_mask_y);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 25672eb..1878038 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -271,6 +271,8 @@ brw_depthbuffer_format(struct brw_context *brw)
  */
 void
 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
+                                uint32_t depth_level,
+                                uint32_t depth_layer,
                                 struct intel_mipmap_tree *stencil_mt,
                                 uint32_t *out_tile_mask_x,
                                 uint32_t *out_tile_mask_y)
@@ -367,7 +369,10 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw,
    }
 
    uint32_t tile_mask_x, tile_mask_y;
-   brw_get_depthstencil_tile_masks(depth_mt, stencil_mt,
+   brw_get_depthstencil_tile_masks(depth_mt,
+                                   depth_mt ? depth_irb->mt_level : 0,
+                                   depth_mt ? depth_irb->mt_layer : 0,
+                                   stencil_mt,
                                    &tile_mask_x, &tile_mask_y);
 
    if (depth_irb) {
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index e6b8485..b6fbd44 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -829,7 +829,10 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
    uint32_t draw_y = params->depth.y_offset;
    uint32_t tile_mask_x, tile_mask_y;
 
-   brw_get_depthstencil_tile_masks(params->depth.mt, NULL,
+   brw_get_depthstencil_tile_masks(params->depth.mt,
+                                   params->depth.level,
+                                   params->depth.layer,
+                                   NULL,
                                    &tile_mask_x, &tile_mask_y);
 
    /* 3DSTATE_DEPTH_BUFFER */
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index bfd2cbd..423dd3c 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -585,7 +585,10 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
    uint32_t tile_mask_x, tile_mask_y;
 
    if (params->depth.mt) {
-      brw_get_depthstencil_tile_masks(params->depth.mt, NULL,
+      brw_get_depthstencil_tile_masks(params->depth.mt,
+                                      params->depth.level,
+                                      params->depth.layer,
+                                      NULL,
                                       &tile_mask_x, &tile_mask_y);
    }
 
-- 
1.8.2.1