[Mesa-dev] [PATCH] i965/gen7: fix 3DSTATE_LINE_STIPPLE_PATTERN

[Chia-I Wu]

The inverse repeat count should taks up bits 31:15 and is in U1.16.  Demos
from mesa/demos seem to render correctly with this change, bu piglit
"linestipple" test still fails.
---
 src/mesa/drivers/dri/i965/brw_misc_state.c |   17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 25672eb..ff19987 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -946,9 +946,20 @@ static void upload_line_stipple(struct brw_context *brw)
    BEGIN_BATCH(3);
    OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2));
    OUT_BATCH(ctx->Line.StipplePattern);
-   tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
-   tmpi = tmp * (1<<13);
-   OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
+
+   if (intel->gen >= 7) {
+      /* in U1.16 */
+      tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
+      tmpi = tmp * (1<<16);
+      OUT_BATCH(tmpi << 15 | ctx->Line.StippleFactor);
+   }
+   else {
+      /* in U1.13 */
+      tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
+      tmpi = tmp * (1<<13);
+      OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor);
+   }
+
    CACHED_BATCH();
 }
 
-- 
1.7.10.4