[Mesa-dev] [PATCH] nv50/ir: handle TGSI_OPCODE_IF(float) properly
Jose Fonseca
jfonseca at vmware.com
Sun Apr 14 04:51:47 PDT 2013
Thanks Christoph. Will do.
Jose
----- Original Message -----
> You can merge this with the original UIF patch if you want.
> ---
> .../drivers/nv50/codegen/nv50_ir_from_tgsi.cpp | 7 ++-----
> .../drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp | 2 +-
> .../drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp | 2 +-
> 3 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
> b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
> index 054c75e..d8abccd 100644
> --- a/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nv50/codegen/nv50_ir_from_tgsi.cpp
> @@ -386,6 +386,7 @@ static nv50_ir::TexTarget translateTexture(uint tex)
> nv50_ir::DataType Instruction::inferSrcType() const
> {
> switch (getOpcode()) {
> + case TGSI_OPCODE_UIF:
> case TGSI_OPCODE_AND:
> case TGSI_OPCODE_OR:
> case TGSI_OPCODE_XOR:
> @@ -2431,10 +2432,6 @@ Converter::handleInstruction(const struct
> tgsi_full_instruction *insn)
> mkOp1(op, TYPE_U32, NULL, src0)->fixed = 1;
> break;
> case TGSI_OPCODE_IF:
> - /* XXX: fall-through into UIF, but this might lead to
> - * incorrect behavior on state trackers and auxiliary
> - * modules that emit float bool IFs regardless of
> - * native integer support */
> case TGSI_OPCODE_UIF:
> {
> BasicBlock *ifBB = new BasicBlock(func);
> @@ -2443,7 +2440,7 @@ Converter::handleInstruction(const struct
> tgsi_full_instruction *insn)
> condBBs.push(bb);
> joinBBs.push(bb);
>
> - mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0));
> + mkFlow(OP_BRA, NULL, CC_NOT_P, fetchSrc(0, 0))->setType(srcTy);
>
> setPosition(ifBB, true);
> }
> diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp
> b/src/gallium/drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp
> index 20f76f8..03086e3 100644
> --- a/src/gallium/drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp
> +++ b/src/gallium/drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp
> @@ -1011,7 +1011,7 @@ NV50LoweringPreSSA::checkPredicate(Instruction *insn)
> return;
> cdst = bld.getSSA(1, FILE_FLAGS);
>
> - bld.mkCmp(OP_SET, CC_NEU, TYPE_U32, cdst, bld.loadImm(NULL, 0), pred);
> + bld.mkCmp(OP_SET, CC_NEU, insn->dType, cdst, bld.loadImm(NULL, 0), pred);
>
> insn->setPredicate(insn->cc, cdst);
> }
> diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
> b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
> index 4d1d372..7676185 100644
> --- a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
> +++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
> @@ -1490,7 +1490,7 @@ NVC0LoweringPass::checkPredicate(Instruction *insn)
> // CAUTION: don't use pdst->getInsn, the definition might not be unique,
> // delay turning PSET(FSET(x,y),0) into PSET(x,y) to a later pass
>
> - bld.mkCmp(OP_SET, CC_NEU, TYPE_U32, pdst, bld.mkImm(0), pred);
> + bld.mkCmp(OP_SET, CC_NEU, insn->dType, pdst, bld.mkImm(0), pred);
>
> insn->setPredicate(insn->cc, pdst);
> }
> --
> 1.7.3.4
>
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