[Mesa-dev] [PATCH 15/16] i965: Lower bitfieldExtract and bitfieldInsert.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_shader.cpp |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index b3bd1b9..15a0440 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -151,6 +151,20 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
        * must precede lower_instructions().
        */
       brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader->ir);
+
+      /* bitfield lowering passes insert subtraction instructions which need
+       * to be lowered, so it must precede lower_instructions(SUB_TO_ADD_NEG).
+       */
+      int bfe_to_bitops = 0, bitfield_insert = 0;
+      if (intel->gen >= 7) {
+         bfe_to_bitops = stage != MESA_SHADER_FRAGMENT
+                         ? BFE_TO_BITOPS : 0;
+         bitfield_insert = stage != MESA_SHADER_FRAGMENT
+                           ? BITFIELD_INSERT_TO_BFM_BITOPS
+                           : BITFIELD_INSERT_TO_BFM_BFI;
+      }
+      lower_instructions(shader->ir, bfe_to_bitops | bitfield_insert);
+
       do_mat_op_to_vec(shader->ir);
       const int lrp_to_arith = (intel->gen < 6 || stage != MESA_SHADER_FRAGMENT)
                                 ? LRP_TO_ARITH : 0;
-- 
1.7.8.6