[Mesa-dev] [PATCH] intel: Be more conservative in disabling tiling to save memory.

[Daniel Vetter]

On Thu, Apr 25, 2013 at 03:41:01PM -0700, Eric Anholt wrote:
> Improves GLB2.7 trex performance 1.01985% +/- 0.721366% on my IVB (n=10)
> and by 3.38771% +/- 0.584241% (n=15) on my HSW, due to a 32x32 ARGB8888
> cubemap going from untiled to tiled.
> ---
>  src/mesa/drivers/dri/intel/intel_mipmap_tree.c |    8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> index 98f1e98..12a4a22 100644
> --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
> @@ -345,11 +345,13 @@ intel_miptree_choose_tiling(struct intel_context *intel,
>          base_format == GL_DEPTH_STENCIL_EXT))
>        return I915_TILING_Y;
>  
> -   /* If the width is smaller than a tile, don't bother tiling. */
> -   if (width0 < 64)
> +   int minimum_pitch = mt->total_width * mt->cpp;
> +
> +   /* If the width is much smaller than a tile, don't bother tiling. */
> +   if (minimum_pitch < 64)
>        return I915_TILING_NONE;

The old limit made sense for X-tiled and dword-size pixels, so shouldn't
we move this around a bit and keep a break of 256b for X-tiled and 64b
when Y-tiling is possible?

Otoh only pre-gen6 would care, so meh. Either way

Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>

>  
> -   if (ALIGN(mt->total_width * mt->cpp, 512) >= 32768) {
> +   if (ALIGN(minimum_pitch, 512) >= 32768) {
>        perf_debug("%dx%d miptree too large to blit, falling back to untiled",
>                   mt->total_width, mt->total_height);
>        return I915_TILING_NONE;
> -- 
> 1.7.10.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch