[Mesa-dev] [PATCH 1/2] R600/SI: Implement sint<->fp64 conversions

[Tom Stellard]

On Wed, Aug 07, 2013 at 05:53:36PM +0200, Niels Ole Salscheider wrote:
> ---
>  lib/Target/R600/SIInstrInfo.td    | 6 ++++++
>  lib/Target/R600/SIInstructions.td | 8 ++++++--
>  test/CodeGen/R600/fp64_to_sint.ll | 9 +++++++++
>  test/CodeGen/R600/sint_to_fp64.ll | 9 +++++++++

Both patches are:

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

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-Tom

>  4 Dateien geändert, 30 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)
>  create mode 100644 test/CodeGen/R600/fp64_to_sint.ll
>  create mode 100644 test/CodeGen/R600/sint_to_fp64.ll
> 
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index 52af79c..302fa24 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -184,6 +184,12 @@ multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern>
>  multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
>    : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
>  
> +multiclass VOP1_32_64 <bits<8> op, string opName, list<dag> pattern>
> +  : VOP1_Helper <op, VReg_32, VSrc_64, opName, pattern>;
> +
> +multiclass VOP1_64_32 <bits<8> op, string opName, list<dag> pattern>
> +  : VOP1_Helper <op, VReg_64, VSrc_32, opName, pattern>;
> +
>  multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
>                          string opName, list<dag> pattern, string revOp> {
>    def _e32 : VOP2 <
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index 500d15e..efe7a3e 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -603,8 +603,12 @@ defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
>  } // End neverHasSideEffects = 1, isMoveImm = 1
>  
>  defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>;
> -//defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>;
> -//defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>;
> +defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64",
> +  [(set i32:$dst, (fp_to_sint f64:$src0))]
> +>;
> +defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32",
> +  [(set f64:$dst, (sint_to_fp i32:$src0))]
> +>;
>  defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32",
>    [(set f32:$dst, (sint_to_fp i32:$src0))]
>  >;
> diff --git a/test/CodeGen/R600/fp64_to_sint.ll b/test/CodeGen/R600/fp64_to_sint.ll
> new file mode 100644
> index 0000000..42f9f34
> --- /dev/null
> +++ b/test/CodeGen/R600/fp64_to_sint.ll
> @@ -0,0 +1,9 @@
> +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
> +
> +; CHECK: @fp64_to_sint
> +; CHECK: V_CVT_I32_F64_e32
> +define void @fp64_to_sint(i32 addrspace(1)* %out, double %in) {
> +  %result = fptosi double %in to i32
> +  store i32 %result, i32 addrspace(1)* %out
> +  ret void
> +}
> diff --git a/test/CodeGen/R600/sint_to_fp64.ll b/test/CodeGen/R600/sint_to_fp64.ll
> new file mode 100644
> index 0000000..37f67c9
> --- /dev/null
> +++ b/test/CodeGen/R600/sint_to_fp64.ll
> @@ -0,0 +1,9 @@
> +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
> +
> +; CHECK: @sint_to_fp64
> +; CHECK: V_CVT_F64_I32_e32
> +define void @sint_to_fp64(double addrspace(1)* %out, i32 %in) {
> +  %result = sitofp i32 %in to double
> +  store double %result, double addrspace(1)* %out
> +  ret void
> +}
> -- 
> 1.7.11.7
> 
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