[Mesa-dev] [PATCH V2 12/12] i965: allow 8 user clip planes on CTG+

[Chris Forbes]

There's no need to use a clip flag for NEGW on these gens, so
no reason we can't just enable 8 planes.

V2: - Bump (and document!) MAX_VERTS in the clip code.
    - Fix clip flag masks in the clip unit state and in the shader
      prolog
    - Move this to the end of the series for less breakage.

Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
---
 src/mesa/drivers/dri/i965/brw_clip.h       | 6 +++++-
 src/mesa/drivers/dri/i965/brw_clip_state.c | 8 +++++++-
 src/mesa/drivers/dri/i965/brw_clip_tri.c   | 4 ++--
 src/mesa/drivers/dri/i965/brw_clip_util.c  | 7 ++++++-
 src/mesa/drivers/dri/i965/brw_context.c    | 2 +-
 5 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h
index 1f6ef39..f26d75d 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.h
+++ b/src/mesa/drivers/dri/i965/brw_clip.h
@@ -36,7 +36,11 @@
 #include "brw_context.h"
 #include "brw_eu.h"
 
-#define MAX_VERTS (3+6+6)	
+/* Initial 3 verts, plus at most 6 additional verts from intersections
+ * with fixed planes, plus at most 8 additional verts from intersections
+ * with user clip planes
+ */
+#define MAX_VERTS (3+6+8)
 
 /* Note that if unfilled primitives are being emitted, we have to fix
  * up polygon offset and flatshading at this point:
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index bb29daf..634719b 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -115,7 +115,13 @@ brw_upload_clip_unit(struct brw_context *brw)
    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
       clip->thread4.stats_enable = 1;
 
-   clip->clip5.userclip_enable_flags = 0x7f;
+   /* _NEW_TRANSFORM */
+   if (brw->gen == 5 || brw->is_g4x)
+      clip->clip5.userclip_enable_flags = ctx->Transform.ClipPlanesEnabled;
+   else
+      /* Up to 6 actual clip flags, plus the 7th for negative RHW workaround. */
+      clip->clip5.userclip_enable_flags = (ctx->Transform.ClipPlanesEnabled & 0x3f) | 0x40;
+
    clip->clip5.userclip_must_clip = 1;
 
    /* enable guardband clipping if we can */
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index 6d0e178..1eeb995 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -282,9 +282,9 @@ void brw_clip_tri( struct brw_clip_compile *c )
    brw_MOV(p, get_addr_reg(freelist_ptr), brw_address(c->reg.vertex[3]) );
 
    /* Set the initial vertex source mask: The first 6 planes are the bounds
-    * of the view volume; the next 6 planes are the user clipping planes.
+    * of the view volume; the next 8 planes are the user clipping planes.
     */
-   brw_MOV(p, c->reg.vertex_src_mask, brw_imm_ud(0xfc0));
+   brw_MOV(p, c->reg.vertex_src_mask, brw_imm_ud(0x3fc0));
 
    /* Set the initial clipdistance offset to be 6 floats before gl_ClipDistance[0].
     * We'll increment 6 times before we start hitting actual user clipping. */
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 2ba4dcb..62172ec 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -420,6 +420,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
 {
    struct brw_compile *p = &c->func;
    struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
+   struct brw_context *brw = p->brw;
    
    /* Shift so that lowest outcode bit is rightmost: 
     */
@@ -431,7 +432,11 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
       /* Rearrange userclip outcodes so that they come directly after
        * the fixed plane bits.
        */
-      brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
+      if (brw->gen == 5 || brw->is_g4x)
+         brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14));
+      else
+         brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
+
       brw_SHR(p, tmp, tmp, brw_imm_ud(8));
       brw_OR(p, c->reg.planemask, c->reg.planemask, tmp);
       
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index a201eed..11d438b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -190,7 +190,7 @@ brw_initialize_context_constants(struct brw_context *brw)
    ctx->Const.MaxPointSizeAA = 255.0;
    ctx->Const.PointSizeGranularity = 1.0;
 
-   if (brw->gen >= 6)
+   if (brw->gen >= 5 || brw->is_g4x)
       ctx->Const.MaxClipPlanes = 8;
 
    ctx->Const.VertexProgram.MaxNativeInstructions = 16 * 1024;
-- 
1.8.3.4