[Mesa-dev] [PATCH 2/3] i965/gen7: Set MOCS L3 cacheability for IVB/BYT

[Chad Versace]

On 08/13/2013 03:31 PM, Vedran Rodic wrote:
> On Mon, Aug 12, 2013 at 3:07 PM,  <ville.syrjala at linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>>
>> IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
>> so let's make use of it.
>
> According to the discussion we had on #intel-gfx a few weeks ago, on
> IVB all Mesa memory is already marked as cached in DRM allocated PTEs.
> So this should not have any effect. Or I'm misunderstanding something.
>
> As I understand, marking everything uncacheable and then marking just
> certain things cacheable could make a difference (since AFAIK, you
> can't mark select regions as uncacheable after you mark PTEs as
> cacheable on IVB).
>
> Can somebody more knowledgeable comment?

On Ivybridge, the PTEs mark only contexts as LLC+L3 cacheable. Everything
else is marked as cacheable in LLC, but not L3. So, Ville's patches will
give a perf boost to Mesa running on any kernel that continues that cacheing
policy.