[Mesa-dev] [PATCH 1/2] i965: Add Gen6 depth stall flushes before disabling depth in BLORP.

[Ian Romanick]

Series is

Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>

On 08/13/2013 12:07 PM, Kenneth Graunke wrote:
> We emit these before configuring depth in the normal path, or actually
> using the depth buffer in BLORP - we just failed to emit them when
> disabling depth altogether.
>
> On Sandybridge, this also requires the post_sync_nonzero flush.
>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>   src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> index a4a9081..129c113 100644
> --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> @@ -914,6 +914,9 @@ static void
>   gen6_blorp_emit_depth_disable(struct brw_context *brw,
>                                 const brw_blorp_params *params)
>   {
> +   intel_emit_post_sync_nonzero_flush(brw);
> +   intel_emit_depth_stall_flushes(brw);
> +
>      BEGIN_BATCH(7);
>      OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
>      OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
>