[Mesa-dev] [PATCH] radeonsi: flush TC at the end of CS

[Marek Olšák]

Please disregard this patch. I didn't mean to send this one.

Marek

On Wed, Aug 28, 2013 at 1:00 AM, Marek Olšák <maraeo at gmail.com> wrote:
> TC can be used for writing and therefore should be flushed.
> ---
>  src/gallium/drivers/radeonsi/r600_hw_context.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c
> index 5631bdb..1fe6814 100644
> --- a/src/gallium/drivers/radeonsi/r600_hw_context.c
> +++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
> @@ -167,7 +167,7 @@ void si_need_cs_space(struct r600_context *ctx, unsigned num_dw,
>         }
>  }
>
> -static void r600_flush_framebuffer(struct r600_context *ctx)
> +static void r600_flush_caches(struct r600_context *ctx)
>  {
>         struct si_pm4_state *pm4;
>
> @@ -188,7 +188,9 @@ static void r600_flush_framebuffer(struct r600_context *ctx)
>                                 S_0085F0_CB6_DEST_BASE_ENA(1) |
>                                 S_0085F0_CB7_DEST_BASE_ENA(1) |
>                                 S_0085F0_DB_ACTION_ENA(1) |
> -                               S_0085F0_DB_DEST_BASE_ENA(1));
> +                               S_0085F0_DB_DEST_BASE_ENA(1) |
> +                               S_0085F0_TC_ACTION_ENA(1) |
> +                               S_0085F0_TCL1_ACTION_ENA(1));
>         si_cmd_flush_and_inv_cb_meta(pm4);
>
>         si_pm4_emit(ctx, pm4);
> @@ -223,7 +225,7 @@ void si_context_flush(struct r600_context *ctx, unsigned flags)
>         }
>  #endif
>
> -       r600_flush_framebuffer(ctx);
> +       r600_flush_caches(ctx);
>
>         /* partial flush is needed to avoid lockups on some chips with user fences */
>         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
> --
> 1.8.1.2
>