[Mesa-dev] [PATCH 06/23] i965: Define common register base class shared between both back-ends.
Francisco Jerez
currojerez at riseup.net
Mon Dec 2 11:31:11 PST 2013
This defines a backend_reg class that contains most of the common
member variables present in the fs and vec4 register classes. It's
simply a location in the register file and doesn't know about indirect
addressing or funky align1/align16 access modes.
Some of the image lowering code coming up is going to be shared
between fs and vec4 so we need some common register representation to
pass values around. The code is complicated enough that I'd hate to
duplicate it [or see someone else duplicate it] just because both
back-ends disagree on the register types.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 32 +++---------
src/mesa/drivers/dri/i965/brw_fs.h | 31 +-----------
src/mesa/drivers/dri/i965/brw_reg.h | 1 +
src/mesa/drivers/dri/i965/brw_shader.cpp | 53 ++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_shader.h | 40 +++++++++++++++
src/mesa/drivers/dri/i965/brw_vec4.cpp | 58 +++++++---------------
src/mesa/drivers/dri/i965/brw_vec4.h | 29 ++---------
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 2 +-
8 files changed, 125 insertions(+), 121 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 37e531d..761e7e6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -425,6 +425,12 @@ fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
this->type = fixed_hw_reg.type;
}
+fs_reg::fs_reg(const backend_reg ®)
+{
+ init();
+ *static_cast<backend_reg *>(this) = reg;
+}
+
bool
fs_reg::equals(const fs_reg &r) const
{
@@ -450,32 +456,6 @@ fs_reg::retype(uint32_t type)
}
bool
-fs_reg::is_zero() const
-{
- if (file != IMM)
- return false;
-
- return type == BRW_REGISTER_TYPE_F ? imm.f == 0.0 : imm.i == 0;
-}
-
-bool
-fs_reg::is_one() const
-{
- if (file != IMM)
- return false;
-
- return type == BRW_REGISTER_TYPE_F ? imm.f == 1.0 : imm.i == 1;
-}
-
-bool
-fs_reg::is_null() const
-{
- return file == HW_REG &&
- fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
- fixed_hw_reg.nr == BRW_ARF_NULL;
-}
-
-bool
fs_reg::is_valid_3src() const
{
return file == GRF || file == UNIFORM;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index f8fb1c5..dfd3b07 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -59,7 +59,7 @@ namespace brw {
class fs_live_variables;
}
-class fs_reg {
+class fs_reg : public backend_reg {
public:
DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
@@ -70,47 +70,20 @@ public:
fs_reg(int32_t i);
fs_reg(uint32_t u);
fs_reg(struct brw_reg fixed_hw_reg);
+ fs_reg(const backend_reg ®);
fs_reg(enum register_file file, int reg);
fs_reg(enum register_file file, int reg, uint32_t type);
fs_reg(class fs_visitor *v, const struct glsl_type *type);
bool equals(const fs_reg &r) const;
- bool is_zero() const;
- bool is_one() const;
- bool is_null() const;
bool is_valid_3src() const;
fs_reg retype(uint32_t type);
- /** Register file: GRF, MRF, IMM. */
- enum register_file file;
- /**
- * Register number. For MRF, it's the hardware register. For
- * GRF, it's a virtual register number until register allocation
- */
- int reg;
- /**
- * Offset from the start of the contiguous register block.
- *
- * For pre-register-allocation GRFs, this is in units of a float per pixel
- * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
- * For uniforms, this is in units of 1 float.
- */
- int reg_offset;
- /** Register type. BRW_REGISTER_TYPE_* */
- int type;
bool negate;
bool abs;
bool sechalf;
- struct brw_reg fixed_hw_reg;
int smear; /* -1, or a channel of the reg to smear to all channels. */
- /** Value for file == IMM */
- union {
- int32_t i;
- uint32_t u;
- float f;
- } imm;
-
fs_reg *reladdr;
};
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h
index 548d677..66f6aad 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -44,6 +44,7 @@
#include <stdbool.h>
#include "program/prog_instruction.h"
+#include "main/compiler.h"
#include "brw_defines.h"
#ifdef __cplusplus
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 6ce7653..8e41160 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -536,6 +536,59 @@ brw_instruction_name(enum opcode op)
}
}
+backend_reg::backend_reg() :
+ file(BAD_FILE),
+ reg(0), reg_offset(0),
+ type(BRW_REGISTER_TYPE_UD),
+ fixed_hw_reg(),
+ imm()
+{
+
+}
+
+backend_reg::backend_reg(struct brw_reg fixed_hw_reg) :
+ file(HW_REG),
+ reg(0), reg_offset(0),
+ type(BRW_REGISTER_TYPE_UD),
+ fixed_hw_reg(fixed_hw_reg),
+ imm()
+{
+}
+
+bool
+backend_reg::is_zero() const
+{
+ if (file != IMM)
+ return false;
+
+ if (type == BRW_REGISTER_TYPE_F) {
+ return imm.f == 0.0;
+ } else {
+ return imm.i == 0;
+ }
+}
+
+bool
+backend_reg::is_one() const
+{
+ if (file != IMM)
+ return false;
+
+ if (type == BRW_REGISTER_TYPE_F) {
+ return imm.f == 1.0;
+ } else {
+ return imm.i == 1;
+ }
+}
+
+bool
+backend_reg::is_null() const
+{
+ return file == HW_REG &&
+ fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ fixed_hw_reg.nr == BRW_ARF_NULL;
+}
+
bool
backend_instruction::is_tex()
{
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index ff5af93..f284389 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -23,6 +23,7 @@
#include <stdint.h>
#include "brw_defines.h"
+#include "brw_reg.h"
#include "glsl/ir.h"
#pragma once
@@ -39,6 +40,45 @@ enum register_file {
#ifdef __cplusplus
+class backend_reg {
+public:
+ backend_reg();
+ backend_reg(struct brw_reg reg);
+
+ bool is_zero() const;
+ bool is_one() const;
+ bool is_null() const;
+
+ /** Register file: GRF, MRF, IMM. */
+ enum register_file file;
+
+ /**
+ * Register number. For MRF, it's the hardware register. For
+ * GRF, it's a virtual register number until register allocation
+ */
+ int reg;
+
+ /**
+ * Offset from the start of the contiguous register block.
+ *
+ * For pre-register-allocation GRFs, this is in units of a float per pixel
+ * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
+ * For uniforms, this is in units of 1 float.
+ */
+ int reg_offset;
+
+ /** Register type. BRW_REGISTER_TYPE_* */
+ int type;
+ struct brw_reg fixed_hw_reg;
+
+ /** Value for file == BRW_IMMMEDIATE_FILE */
+ union {
+ int32_t i;
+ uint32_t u;
+ float f;
+ } imm;
+};
+
class backend_instruction : public exec_node {
public:
bool is_tex();
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 7b9fbf1..e149f39 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -120,21 +120,23 @@ src_reg::src_reg(struct brw_reg reg)
this->fixed_hw_reg = reg;
}
-src_reg::src_reg(dst_reg reg)
+src_reg::src_reg(const backend_reg ®)
{
init();
+ *static_cast<backend_reg *>(this) = reg;
+ this->swizzle = BRW_SWIZZLE_XYZW;
+}
- this->file = reg.file;
- this->reg = reg.reg;
- this->reg_offset = reg.reg_offset;
- this->type = reg.type;
- this->reladdr = reg.reladdr;
- this->fixed_hw_reg = reg.fixed_hw_reg;
-
+src_reg::src_reg(dst_reg reg)
+{
int swizzles[4];
int next_chan = 0;
int last = 0;
+ init();
+ *static_cast<backend_reg *>(this) = reg;
+ this->reladdr = reg.reladdr;
+
for (int i = 0; i < 4; i++) {
if (!(reg.writemask & (1 << i)))
continue;
@@ -190,14 +192,18 @@ dst_reg::dst_reg(struct brw_reg reg)
this->fixed_hw_reg = reg;
}
+dst_reg::dst_reg(const backend_reg ®)
+{
+ init();
+ *static_cast<backend_reg *>(this) = reg;
+}
+
dst_reg::dst_reg(src_reg reg)
{
init();
+ *static_cast<backend_reg *>(this) = reg;
+ this->reladdr = reg.reladdr;
- this->file = reg.file;
- this->reg = reg.reg;
- this->reg_offset = reg.reg_offset;
- this->type = reg.type;
/* How should we do writemasking when converting from a src_reg? It seems
* pretty obvious that for src.xxxx the caller wants to write to src.x, but
* what about for src.wx? Just special-case src.xxxx for now.
@@ -206,8 +212,6 @@ dst_reg::dst_reg(src_reg reg)
this->writemask = WRITEMASK_X;
else
this->writemask = WRITEMASK_XYZW;
- this->reladdr = reg.reladdr;
- this->fixed_hw_reg = reg.fixed_hw_reg;
}
bool
@@ -476,32 +480,6 @@ vec4_visitor::pack_uniform_registers()
}
}
-bool
-src_reg::is_zero() const
-{
- if (file != IMM)
- return false;
-
- if (type == BRW_REGISTER_TYPE_F) {
- return imm.f == 0.0;
- } else {
- return imm.i == 0;
- }
-}
-
-bool
-src_reg::is_one() const
-{
- if (file != IMM)
- return false;
-
- if (type == BRW_REGISTER_TYPE_F) {
- return imm.f == 1.0;
- } else {
- return imm.i == 1;
- }
-}
-
/**
* Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
*
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 3b3f35b..a718333 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -89,28 +89,7 @@ class dst_reg;
unsigned
swizzle_for_size(int size);
-class reg
-{
-public:
- /** Register file: GRF, MRF, IMM. */
- enum register_file file;
- /** virtual register number. 0 = fixed hw reg */
- int reg;
- /** Offset within the virtual register. */
- int reg_offset;
- /** Register type. BRW_REGISTER_TYPE_* */
- int type;
- struct brw_reg fixed_hw_reg;
-
- /** Value for file == BRW_IMMMEDIATE_FILE */
- union {
- int32_t i;
- uint32_t u;
- float f;
- } imm;
-};
-
-class src_reg : public reg
+class src_reg : public backend_reg
{
public:
DECLARE_RALLOC_CXX_OPERATORS(src_reg)
@@ -123,10 +102,9 @@ public:
src_reg(uint32_t u);
src_reg(int32_t i);
src_reg(struct brw_reg reg);
+ src_reg(const backend_reg ®);
bool equals(src_reg *r);
- bool is_zero() const;
- bool is_one() const;
src_reg(class vec4_visitor *v, const struct glsl_type *type);
@@ -139,7 +117,7 @@ public:
src_reg *reladdr;
};
-class dst_reg : public reg
+class dst_reg : public backend_reg
{
public:
DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
@@ -151,6 +129,7 @@ public:
dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
dst_reg(struct brw_reg reg);
dst_reg(class vec4_visitor *v, const struct glsl_type *type);
+ dst_reg(const backend_reg ®);
explicit dst_reg(src_reg reg);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 95c8d9f..951560b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -34,7 +34,7 @@ using namespace brw;
namespace brw {
static void
-assign(unsigned int *reg_hw_locations, reg *reg)
+assign(unsigned int *reg_hw_locations, backend_reg *reg)
{
if (reg->file == GRF) {
reg->reg = reg_hw_locations[reg->reg];
--
1.8.3.4
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